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| Creator | Title | Description | Subject | Date | ||
|---|---|---|---|---|---|---|
| 1 |
 | Carter, John B. | Avalanche: A communication and memory architecture for scalable parallel computing | As the gap between processor and memory speeds widens, system designers will inevitably incorporate increasingly deep memory hierarchies to maintain the balance between processor and memory system performance. At the same time, most communication subsystems are permitted access only to main memory ... | Avalanche; Computer memory; Memory architecture | 1995 |
| 2 |
 | Weinstein, David | Cache-rings for memory efficient isosurface construction | Processor speeds continue to increase at faster rates than memory speeds. As this performance gap widens, it becomes increasingly important to develop "memory-conscious" algorithms - programs that still optimize instruction count and algorithmic complexity, but that also integrate optimizations for ... | Processor speeds; Memory speeds; Computer memory; Cache-rings | 1997 |
| 3 |
 | Harrison, Reid R. | CMOS programmable analog memory-cell array using floating-gate circuits | The complexity of analog VLSI systems is often limited by the number of pins on a chip rather than by the die area. Currently, many analog parameters and biases are stored off-chip. Moving parameter storage on-chip could save pins and allow us to create complex programmable analog systems. In this ... | Computer chips; VLSI; Computer memory; Potentiometers; CMOS circuits; Floating gate circuit | 2001-01 |
| 4 |
 | Chatterjee, Prosenjit; Gopalakrishnan, Ganesh | Formally specifying memory consistency models and automatically generating executable specifications | Memory ordering properties of shared memory multiprocessors are more subtle and less well understood than cache coherence. These properties tend to be processor or platform specific and are not always formally specified. It is difficult to compare even those platforms whose memory ordering propert... | Computer memory; Memory consistency models; Memory ordering; Shared memory multiprocessors | 2001 |
| 5 |
 | Stoller, Leigh B. | Message passing support in the Avalanche widget | Minimizing communication latency in message passing multiprocessing systems is critical. An emerging problem in these systems is the latency contribution costs caused by the need to percolate the message through the memory hierarchy (at both sending and receiving nodes) and the additional cost of ma... | Avalanche widget; Message passing; Cache coherence; Message copying; Cache miss rates; Computer memory | 1996 |
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