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 | Balasubramonian, Rajeev | Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0 | A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, and thermal management strategies. There are a number of interconnect design considerations that influence power/performanc... | CACTI 6.0; Non-uniform cache architectures (NUCA); Cache models; Memory hierarchies; On-chip interconnects | 2007-12 |
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