TO
1 - 25 of 2
| Creator | Title | Description | Subject | Date | ||
|---|---|---|---|---|---|---|
| 1 |
 | Balasubramonian, Rajeev | Architecting efficient interconnects for large caches with CACTI 6.0 | Efficiently executing multithreaded applications on future multicores will require fast intercore communication. Most of this communication happens via reads and writes to large shared caches in the memory hierarchy. Microprocessor performance and power will be strongly influenced by the long inter... | Interconnects; CACTI 6.0; Non-uniform cache architectures (NUCA) | 2008-01 |
| 2 |
 | Balasubramonian, Rajeev | Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0 | A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, and thermal management strategies. There are a number of interconnect design considerations that influence power/performanc... | CACTI 6.0; Non-uniform cache architectures (NUCA); Cache models; Memory hierarchies; On-chip interconnects | 2007-12 |
1 - 25 of 2