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![]() | Balasubramonian, Rajeev | Understanding the impact of 3D stacked layouts on ILP | 3D die-stacked chips can alleviate the penalties imposed by long wires within micro-processor circuits. Many recent studies have attempted to partition each microprocessor structure across three dimensions to reduce their access times. In this paper, we implement each microprocessor structure on a s... | 2007-01-01 |