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UScholar Works
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Title
Date
Type
1
A DRAM backend for the impulse memory system
1998-12-16
Text
2
A case for increased operating system support in chip multi-processors
2005
Text
3
A case for increased operating system support in chip multi-processors
2005
Text
4
A collective approach to harness idle resources
2008
Text
5
A characterization of visual feature recognition
2003-09-03
Text
6
A correctness criterion for asynchronous circuit validation and optimization
1992
Text
7
A correctness criterion for asynchronous circuit validation and optimization
1992
Text
8
A cell set for self-timed design using actel FPGAs
1991
Text
9
A compositional model for synchronous VLSI systems
1987
Text
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