UScholar Works
 
Filters: Department: "School of Computing" Collection: "ir_uspace"
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CreatorTitleDescriptionSubjectDate
1 Gopalakrishnan, GaneshA correctness criterion for asynchronous circuit validation and optimizationWe propose a new relation C. called strong conformance in the context of Dill's trace theory, and define B Q A to be true exactly when B conforms to A and the success set of B contains the success set of A. When B C. A, module B operated in module A's maximal environment AM (i.e. B || AM) exhibits a...Validation; Optimization1992
2 Bhanu, Bir3-D model building for computer visionThis paper presents a Computer-Aided Geometric Design (CAGD) based approach for building 3-D models which can be used for the recognition of 3-D objects for industrial machine vision applications. The objects are designed using the Alpha_1 CAGD system developed at the University of Utah. A new metho...CAGD; 3-D models; Machine vision1985
3 Brunvand, Erik L.A correctness criterion for asynchronous circuit validation and optimizationIn order to reason about the correctness of asynchronous circuit implementations and specifications, Dill has developed a variant of trace theory [1]. Trace theory describes the behavior of an asynchronous circuit by representing its possible executions as strings called "traces" A useful relatio...Asynchronous circuits; Circuit optimizations; Formal verification of hardware; Trace theory; Asynchronous circuit validation1992
4 Barsky, Brian A.A description of several tools for the synchronization of concurrent processesConcurrent processes are tasks which may be executed simultaneously. When several such processes have access to shared variables, it is necessary to establish some regimen to control this access. Several language tools for expressing various synchronization disciplines are presented.Concurrent processes1980
5 Brunvand, Erik L.A comparison of modular self-timed design stylesState-machine sequencing methods in modular 2-phase and 4-phase asynchronous handshake control are compared. Design styles are discussed, and the sequencers are tested against each other using a medium-scale minicomputer test design implemented in FPGAs. Seven 4-phase sequencers are tested. In these...Self-timed; State-machine sequencing; Asynchronous handshake control1995
6 Mecklenburg, RobertA dossier driven persistent objects facilityWe describe the design and implementation of a persistent object storage facility based on a dossier driven approach. Objects are characterized by dossiers which describe both their language defined and "extra-linguistic" properties. These dossiers are generated by a C+-f- preprocessor in concert ...Persistent object storage facility; Dossier driven1994
7 Brunvand, Erik L.; Smith, Kent F.A comparison of self-timed design using FPGA, CMOS, and GaAs technologiesAsynchronous or self-timed systems that do not rely on U global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in a variety of applications. One advantage is that because of the separation of timing, from, functionality in these sys...1992
8 Panangaden, PrakashA category theoretic formalism for abstract interpretationWe present a formal theory of abstract interpretation based on a new category theoretic formalism. This formalism allows one to derive a collecting semantics which preserves continuity of lifted functions and for which the lifting functon is itself continuous. The theory of abstract interpretation i...Formal theory; Theoretic formalism; Lifted functions1984
9 Gooch, Amy A.; Gooch, Bruce; Willemsen, Peter; Kniss, Joe; Riesenfeld, Richard F.; Shirley, Peter S.3D Line textures and the visualization of confidence in ArchitectureThis work introduces a technique for interactive walkthroughs of non-photorealistically rendered (NPR) scenes using 3D line primitives to define architectural features of the model, as well as indicate textural qualities. Line primitives are not typically used in this manner in favor of texture ma...Presentation graphics; Interactive walkthroughs2007
10 Sobh, Tarek M.A dynamic framework for intelligent inspectionCAD (Computer Aided Design) typically involves the design, manufacture and inspection of a mechanical part. The problem of reverse engineering is to take an existing mechanical part as the point of departure and to inspect or produce a design, and perhaps a manufacturing process, for the part. We pr...CAD; Discrete event dynamic systems; DEDS1992
11 Poeppelmeier, Charles ChristianA boolean sum interpolation scheme to random data for computer aided geometric designThis thesis presents a new imterpolation function for randomly distributed data. The new interpolation function is capable of exactly reproducing quadratic surfaces. The new function is developed, through boolean sum theory, from Shepard's two dimensional interpolation functions and the Barnhill-Gre...Computer-aided geometric design; CAGD; Barnhill-Gregory; Interpolation functions1975
12 McDirmid, Sean; Eide, Eric Norman; Hsieh, Wilson C.A comparison of Jiazzi and AspectJ for feature-wise decompositionFeature-wise decomposition is an important approach to building configurable software systems. Although there has been research on the usefulness of particular tools for featurewise decomposition, there are not many informative comparisons on the relative effectiveness of different tools. In this...Jiazzi; AspectJ; Feature-wise decomposition2004-03-23
13 Mathew, Binu K.; Davis, AlA characterization of visual feature recognitionNatural human interfaces are a key to realizing the dream of ubiquitous computing. This implies that embedded systems must be capable of sophisticated perception tasks. This paper analyzes the nature of a visual feature recognition workload. Visual feature recognition is a key component of a numb...Visual feature recognition; Human interfaces2003-09-03
14 Gopalakrishnan, GaneshA compositional model for synchronous VLSI systemsCurrently available hardware specification languages have two serious deficiencies: (i) inadequate protocol definition capabilities; (ii) lack of a compositional model. We now explain these in more detail.Very large scale integration; VLSI systems1987
15 Brunvand, Erik L.A case for increased operating system support in chip multi-processorsWe identify the operating system as one area where a novel architecture could significantly improve on current chip multi-processor designs, allowing increased performance and improved power efficiency. We first show that the operating system contributes a non-trivial overhead to even the most com...2005
16 Balasubramonian, RajeevA case for increased operating system support in chip multi-processorsWe identify the operating system as one area where a novel architecture could significantly improve on current chip multi-processor designs, allowing increased performance and improved power efficiency. We first show that the operating system contributes a non-trivial overhead to even the most com...2005
17 A distributed garbage collection algorithmConcurrent Scheme extends the Scheme programming language, providing parallel program execution on a distributed network. The Concurrent Scheme environment requires a garbage collector to reclaim global objects; objects that exist in a portion of the global heap located on the node that created them...Concurrent Scheme; Garbage collection algorithm1992
18 Brunvand, Erik L.A cell set for self-timed design using actel FPGAsAsynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in a variety of applications. However, these systems require that suitable self-timed circuit primitives are available for b...Self-timed systems; Actel field programmable gate arrays; FPGA1991
19 Carter, JohnA collective approach to harness idle resourcesWe propose a collective approach for harnessing the idle resources (cpu, storage, and bandwidth) of nodes (e.g., home desktops) distributed across the Internet. Instead of a purely peer-to-peer (P2P) approach, we organize participating nodes to act collectively using collective managers (CMs). Pa...Idle resources; Computer nodes2008
20 Evans, John; Kessler, Robert R.A communication-ordered task graph allocation algorithmThe inherently asynchronous nature of the data flow computation model allows the exploitation of maximum parallelism in program execution?? While this computational model holds great promise several problems must be solved in order to achieve a high degree of program performance?? The allocation...Data flow computation model1992
21 Zhang, LixinA comparison of online superpage promotion mechanismsThe amount of data that a typical translation lookaside buffer (TLB) can map has not kept pace with the growth in cache sizes and application footprints. As a result, the cost of handling TLB misses limits the performance of an increasing number of applications. The use of superpages, multiple adjac...Superpages; Translation lookaside buffer; TLB1999
22 Kessler, Robert R.A communication-ordered task graph allocation algorithmThe inherently asynchronous nature of the data flow computation model allows the exploitation of maximum parallelism in program execution. While this computational model holds great promise, several problems must be solved in order to achieve a high degree of program performance. The allocation and ...Task graph allocation algorithm1992
23 Henderson, Thomas C.2-D scene analysis using split-level relaxationWe present a new method for applying multiple semantic constraints based on discrete relaxation. A separate graph is maintained for each constraint relation and used in parallel to achieve a consistent labeling. This permits both local and global analysis without recourse to complete graphs. Here l...Discrete relaxation; Split-level relaxation1985
24 Carter, John B.A comparison of software and hardware synchronization mechanisms for distributed shared memory multiprocessorsEfficient synchronization is an essential component of parallel computing. The designers of traditional multiprocessors have included hardware support only for simple operations such as compare-and-swap and load-linked/store-conditional, while high level synchronization primitives such as locks, bar...Hardware locks1996
25 Zhang, LixinA DRAM backend for the impulse memory systemThe Impulse Adaptable Memory System exposes DRAM access patterns not seen in conventional memory systems. For instance, it can generate 32 DRAM accesses each of which requests a four-byte word in 32 cycles. Conventional DRAM backends are optimized for accesses that request full cache lines. They m...Impulse Adaptable Memory System; DRAM1998-12-16
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