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| Creator | Title | Description | Subject | Date | ||
|---|---|---|---|---|---|---|
| 1 |
 | Carter, Tony M. | Path-programmable logic | Path-Programmable Logic (PPL) is a structured IC design methodology under development at the University of Utah. PPL employs a sea-of-wires approach to design. In PPL, design is done entirely using cells for both functionality and interconnect. PPL cells may have modifiers that change either their ... | Path-Programmable Logic; PPL | 1989 |
| 2 |
 | Smith, Kent F. | Tiler user's guide | Tiler is a special interactive editor used for designing VLSI circuits using the Path Programmable Logic (PPL) methodology. PPL cells are inserted into a rectangular grid by typing characters that represent the cells. Each available cell will have a character that represents it, but some characters ... | Tiler; Interactive editor; VLSI circuits; Design; Path Programmable Logic; PPL | 1986 |
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