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 | Chatterjee, Niladrish; Balasubramonian, Rajeev; Davis, Alan L. | Rethinking DRAM design and organization for energy-constrained multicores | DRAM vendors have traditionally optimized for low cost and high performance, often making design decisions that incur energy penalties. For example, a single conventional DRAM access activates thousands of bitlines in many chips, to return a single cache line to the CPU. The other bits may be access... | DRAM power consumption; Data-center power; Multicore memory; Trapeze Interactive Poster | 2010-03-15 |