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 | Balasubramonian, Rajeev | CHOP: adaptive filter-based DRAM caching for CMP server platforms | As manycore architectures enable a large number of cores on the die, a key challenge that emerges is the availability of memory bandwidth with conventional DRAM solutions. To address this challenge, integration of large DRAM caches that provide as much as 5× higher bandwidth and as low as 1/3rd of... | CHOP; DRAM caching; CMP server platforms; Manycore architectures; Hot page; Filter cache; Multi-core processors | 2010 |
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 | Balasubramonian, Rajeev | Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy | Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postulate a 3D chip design that stacks SRAM and DRAM upon processing cores and employs OS-based page coloring to minimize hori... | Multi-core processors; Cache and memory hierarchy; Non-uniform cache architecture (NUCA); Page coloring; On-chip networks; SRAM/DRAM cache reconfiguration | 2009-02 |