1 - 25 of 2
Number of results to display per page
CreatorTitleDescriptionSubjectDate
1 Balasubramonian, RajeevCHOP: adaptive filter-based DRAM caching for CMP server platformsAs manycore architectures enable a large number of cores on the die, a key challenge that emerges is the availability of memory bandwidth with conventional DRAM solutions. To address this challenge, integration of large DRAM caches that provide as much as 5× higher bandwidth and as low as 1/3rd of...CHOP; DRAM caching; CMP server platforms; Manycore architectures; Hot page; Filter cache; Multi-core processors2010
2 Balasubramonian, RajeevOptimizing communication and capacity in a 3D stacked reconfigurable cache hierarchyCache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postulate a 3D chip design that stacks SRAM and DRAM upon processing cores and employs OS-based page coloring to minimize hori...Multi-core processors; Cache and memory hierarchy; Non-uniform cache architecture (NUCA); Page coloring; On-chip networks; SRAM/DRAM cache reconfiguration2009-02
1 - 25 of 2