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 | Balasubramonian, Rajeev | Re-visiting the performance impact of microarchitectural floorplanning | The placement of microarchitectural blocks on a die can significantly impact operating temperature. A floorplan that is optimized for low temperature can negatively impact performance by introducing wire delays between critical pipeline stages. In this paper, we identify subsets of wire delays tha... | Microarchitectural floorplanning; Wire delays; Floorplanning algorithms; Microprocessor operating temperature; Critical loops; Pipelines | 2006 |