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| Creator | Title | Description | Subject | Date | ||
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 | Balasubramonian, Rajeev | Microarchitectural wire management for performance and power in partitioned architectures | Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low power. In such architectures, inter-partition communication over global wires has a significant impact on overall proc... | Microarchitecture; Partitioned architectures; Heterogeneous interconnects; Cache access | 2005 |
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