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1 Myers, Chris J.; Harrison, Reid R.; Schlegel, ChristianCell library for automatic synthesis of analog error control decodersThis paper presents a cell library for automatic synthesis of analog error control decoders. By using some basic cells, analog ermr control decoders can be automatically synthesized. Also, using automatic synthesis based on this cell library, the circuit performance is not degraded and the circuit i...2002
2 Myers, Chris J.Technology mapping of timed circuitsAbstract This paper presents an automated procedure for the technology mapping of timed circuits to practical gate libraries. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the design process to optimi...1995
3 Harrison, Reid R.; Myers, Chris J.; Schlegel, ChristianCell library for automatic synthesis of analog error control decodersThis paper presents a cell library for automatic synthesis of analog error control decoders. By using some basic cells, analog ermr control decoders can be automatically synthesized. Also, using automatic synthesis based on this cell library, the circuit performance is not degraded and the circuit i...2002
4 Stevens, KennethRadiation hardening by design of asynchronous logic for hostile environmentsA wide range of emerging applications is driving the development of wireless sensor node technology towards a monolithic system-on-a-chip implementation. Of particular interest are hostile environment scenarios where radiation and thermal extremes exist. Radiation hardening by design has been recogn...2009
5 Stevens, KennethAutomatic addition of reset in asynchronous sequential control circuitsAsynchronous finite state machines (AFSMs) usually require initialization to place them in a desired starting state. This normally occurs by toggling a reset signal upon power-up. This paper presents an algorithm to automatically generate power-up reset circuitry thus adding reset to an AFSM after t...2014-01-01
6 Stevens, KennethA mathematical approach to a low power FFT architectureArchitecture and circuit design are the two most effective means of reducing power in CMOS VLSI. Mathematical manipulations have been applied to create a power efficient architecture of an FFT. This architecture has been implemented in asynchronous circuit technology that achieves significant powe...1998
7 Stevens, KennethA single chip low power asynchronous implementation of an FFT algorithm for space applicationsA fully asynchronous _x000C_fixed point FFT processor is introduced for low power space applications. The architecture is based on an algorithm developed by Suter and Stevens specifi_x000C_cally for a low power implementation. The novelty of this architecture lies in its high localization of compo...1998
8 Stevens, KennethAlgorithms for MIS vector generation and pruningIgnoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. The main reason to omit this effect is the run time penalty and potential over-conservatism. Run times are directly proportional to the vector sizes. Efficient algorithm...2006
9 Stevens, KennethDynamic gates with hysteresis and configurable noise toleranceDynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suffered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is prese...2007
10 Furse, Cynthia M.Teaching and learning combined (TLC)Most professors have to lean a LOT. Every day, it seems, there IS something that we need that we don't know. So what do you do to lean this new information? Perhaps you hit the Web or the library, find a tutorial, a textbook, or a paper, and give it a little reading time in between a 12:00 class an...2003
11 Stevens, KennethCharacterization of asynchronous templates for integration into clocked CAD flowsAsynchronous circuit design can result in substantial benefits of reduced power, improved performance, and high modularity. However, asynchronous design styles are largely incompatible with clocked CAD, which has prevented wide-scale adoption. The key incompatibility is timing. Thus most commercial...2009
12 Stevens, KennethComparing energy and latency of asynchronous and synchronous NoCs for embedded SoCsPower consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous network on-chip implementations, optimized for a number of SoC designs. We...2010
13 Myers, Chris J.Architectural synthesis of timed asynchronous systemsThis paper describes a new method for architectural synthesis of timed asynchronous systems. Due to the variable delays associated with asynchronous resources, implicit schedules are created by the addition of supplementary constraints between resources. Since the number of schedules grows exponenti...1999
14 Myers, Chris J.Efficient verification of hazard-freedom in gate-level timed asynchronous circuitsAbstract-This paper presents an efficient method for verifying hazard-freedom in gate-level timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that are optimized using explicit timing information. In asynchronous circuits, correct operation requires that there are no ha...2007
15 Stevens, KennethClocked and asynchronous FIFO characterization and comparisonHeterogeneous blocks, IP reuse, network-on-chip interconnect, and multi-frequency design are becoming more prevalent in integrated circuit design. Communication amongst these blocks typically employs first-in-first-out (FIFO) buffering for flow control. This paper characterizes and evaluates severa...2009
16 Stevens, KennethTotal ionizing dose characterization of a commercially fabricated asynchronous FFT for space applicationsThe total ionizing dose characterization of the radiation-hardened implementation of a novel architecture for high-performance, energy efficiency FFT engines is presented. Simulations and test chip measurement results indicate that a radiation-tolerant 1024-point FFT based on this architecture will...2000
17 Harrison, Reid R.Biologically inspired analog IC for visual collision detectionWe have designed and tested a single-chip analog VLSI sensor that detects imminent collisions by measuring radially expanding optic flow. The design of the chip is based on a model proposed to explain leg-extension behavior in flies during landing approaches. We evaluated a detailed version of thi...Visual collision detection; VLSI2005-11
18 Tasdizen, Tolga; Jones, Bryan W.; Whitaker, Ross T.Computational framework for ultrastructural mapping of neural circuitryCircuitry mapping of metazoan neural systems is difficult because canonical neural regions (regions containing one or more copies of all components) are large, regional borders are uncertain, neuronal diversity is high, and potential network topologies so numerous that only anatomical ground truth c...2009
19 Stevens, KennethSymbolic verification of timed asynchronous hardware protocolsCorrect interaction of asynchronous protocols re- quires verification. Timed asynchronous protocols add another layer of complexity to the verification challenge. A methodology and automated tool flow have been developed for verifying systems of timed asynchronous circuits through compositional mode...2013-01-01
20 Stevens, KennethCA-BIST for asynchronous circuits: a case study on the RAPPID asynchronous instruction length decoderThis paper presents a case study in low-cost noninvasive Built-In Self Test (BIST) for RAPPID, a largescale 120,000-transistor asynchronous version of the Pentium® Pro Instruction Length Decoder, which runs at 3.6 GHz. RAPPID uses a synchronous 0.25 micron CMOS library for static and domino lo...2000
21 Stevens, KennethNetwork simplicity for latency insensitive coresIn this paper we examine a latency insensitive net- work composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asynchronous. These types of cores provide native flow control that is compatible with this network, thus reducing ad...2008
22 Blair, StevenA methodology for physical design automation for integrated opticsAdvancements in silicon photonics technology are enabling large scale integration of electro-optical circuits and systems. To fully exploit this potential, automated techniques for design space exploration and physical synthesis for integrated optics must be developed. This paper investigates how co...2012-01-01
23 Furse, Cynthia M.13 crazy, notorious things to do in an EM classThe average attention span of an adult human is 12-20 minutes. Our lectures are 50-80 minutes. Attention Span Math reminds us to take a break now and then, and to bring the class back to life by bringing some life to the class. Many students learn things better if they can see and touch them, so thi...Attention span; Fun2005-06
24 Stevens, KennethConcurrency reduction of untimed latch protocols - theory and practiceA systematic investigation into concurrency reduction of untimed asynchronous 4-phase latch controllers is reported. Starting with a state graph that exhibits maximal concurrency, rules are provided for systematically reducing its states and thereby curtailing its behaviors. The rules predict liven...2010
25 Myers, Chris J.Design of a genetic muller C-elementSynthetic biology uses engineering principles to design circuits out of genetic materials that are inserted into bacteria to perform various tasks. While synthetic combinational Boolean logic gates have been constructed, there are many open issues in the design of sequential logic gates. One such g...2007
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