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1 Stevens, KennethAn A-FPGA architecture for relative timing based asynchronous designsThis paper presents an asynchronous FPGA architecture that is capable of implementing relative timing based asynchronous designs. The architecture uses the Xilinx 7-Series architecture as a starting point and proposes modifications that would make it asynchronous design capable while keeping it full...2014-01-01
2 Myers, Chris J.An asynchronous implementations of the MAXLIST algorithmABSTRACT We present an efficient asynchronous VLSI architecture for calculating running maximum or minimum values over a sliding window. Running maximums or minimums are very useful for many signal and image processing tasks. Our architecture performs the calculation using the MAXLIST algorithm. In...1997
3 Stevens, KennethA mathematical approach to a low power FFT architectureArchitecture and circuit design are the two most effective means of reducing power in CMOS VLSI. Mathematical manipulations have been applied to create a power efficient architecture of an FFT. This architecture has been implemented in asynchronous circuit technology that achieves significant powe...1998
4 Normann, Richard A.; Johansson,Torbjorn; Abbasi, Masoud; Huber, Robert J.Three-dimensional architecture for a parallel processing photosensing arrayA three-dimensional architecture for a photosensing array has been developed. This silicon based architecture consists of a 10 x 10 array of photosensors with 80 microns diameter, through chip interconnects to the back side of a 500 microns thick silicon wafer. Each photosensor consists of a 300 x 3...Retina; Optics; Silicon; Photosensing1992
5 Stevens, KennethMultirate as a hardware paradigmArchitecture and circuit design are the two most effective means of reducing power in CMOS VLSI. Mathematical manipulations, based on applying ideas from multirate signal processing have been applied to create high performance, low power architectures. To illustrate this approach, two case studies...1999
6 Stevens, KennethTotal ionizing dose characterization of a commercially fabricated asynchronous FFT for space applicationsThe total ionizing dose characterization of the radiation-hardened implementation of a novel architecture for high-performance, energy efficiency FFT engines is presented. Simulations and test chip measurement results indicate that a radiation-tolerant 1024-point FFT based on this architecture will...2000
7 Tasdizen, TolgaUsing sequential context for image analysisThis paper proposes the sequential context inference (SCI) algorithm for Markov random field (MRF) image analysis. This algorithm is designed primarily for fast inference on an MRF model, but its application requires also a specific modeling architecture. The architecture is composed of a sequence ...2010
8 Stevens, KennethA single chip low power asynchronous implementation of an FFT algorithm for space applicationsA fully asynchronous _x000C_fixed point FFT processor is introduced for low power space applications. The architecture is based on an algorithm developed by Suter and Stevens specifi_x000C_cally for a low power implementation. The novelty of this architecture lies in its high localization of compo...1998
9 Myers, Chris J.A standard-cell self-timed multiplier for energy and area critical synchronous systemsThis paper describes the design of a standard-cell self-timed multiplier for use in energy and area critical synchronous systems. The area of this multiplier is bounded by N rather than N2 as seen in more traditional combinational parallel array designs, where N is the word size. Energy has a polyn...2001
10 Normann, Richard A.; Abbasi, Masoud; Johansson,TorbjornSilicon carbide enhanced thermomigrationThe widespread acceptance of thermomigration technology to produce through-chip interconnects has been impaired by (i) a random walk of the Si-Al liquid eutectic inclusion as it traverses the wafer, and (ii) a ?surface barrier? which allows thermomigration of only relatively large inclusions. In ...Silicon Dioxide; Thermometers; Transducers; Thermomigration Technology; Infrared Lamps1992
11 Mastrangelo, Carlos H.Design and characterization of electronic sensing system for a 13 × 13 biomechanical ground reaction sensor arrayThis paper presents the design and characterization of an electronic sensing system interfaced with a high-density flexible biomechanical ground reaction sensor array (GRSA). The prototype system can be incorporated into a personal boot heel to measure real-time ground force, shear strain and sole d...2013-01-01
12 Stevens, KennethCA-BIST for asynchronous circuits: a case study on the RAPPID asynchronous instruction length decoderThis paper presents a case study in low-cost noninvasive Built-In Self Test (BIST) for RAPPID, a largescale 120,000-transistor asynchronous version of the Pentium® Pro Instruction Length Decoder, which runs at 3.6 GHz. RAPPID uses a synchronous 0.25 micron CMOS library for static and domino lo...2000
13 Stevens, KennethComparing energy and latency of asynchronous and synchronous NoCs for embedded SoCsPower consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous network on-chip implementations, optimized for a number of SoC designs. We...2010
14 Furse, Cynthia M.; Harrison, Reid R.Low-power STDR CMOS sensor for locating faults in aging aircraft wiringA CMOS sensor used to locate intermittent faults on live aircraft wires is presented. A novel architecture was developed to implement the Sequence Time Domain Reflectometry method on a 0.5- m integrated circuit. The sensor locates short or open circuits on active wires with an accuracy of +/-1 ft w...Aging aircraft wire; CMOS sensors; Fault detection; Pseudo-random noise; Reflectometry methods; Spread spectrum; Wire fault location2006-01-01
15 Harrison, Reid R.Low-power STDR CMOS sensor for locating faults in aging aircraft wiringA CMOS sensor used to locate intermittent faults on live aircraft wires is presented. A novel architecture was developed to implement the Sequence Time Domain Reflectometry method on a 0.5- m integrated circuit. The sensor locates short or open circuits on active wires with an accuracy of +/-1 ft w...CMOS sensor; Pseudo-random noise; Reflectometry Methods; Spread spectrum; Wire fault location; Time Domain Vernier (TDV) method2007-01
16 Stevens, KennethCAD directions for high performance asynchronous circuitsThis paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This methodology was developed for a prototype iA32 instruction length decoding and steering unit called RAPPID ("Revolving Asynchro...1999
17 Khan, Faisal HabibFabrication processes and experimental validation of a planar PV power system with monolithically embedded power convertersThis paper summarizes the research outcome intended to identify the most suitable device architecture and its implementation for cell-level power conversion in a photovoltaic (PV) system. The fabrication process to accommodate the power conditioning unit with the PV cells using the same process run ...2012-01-01
18 Stevens, KennethBandwidth optimization in asynchronous NoCs by customizing link wire lengthThe bandwidth requirement for each link on a network-on-chip (NoC) may differ based on topology and traffic properties of the IP cores. Available bandwidth on an asynchronous NoC link will also vary depending on the wire length between sender and receiver. We explore the benefit to NoC performance ...2010
19 Stevens, KennethRadiation hardening by design of asynchronous logic for hostile environmentsA wide range of emerging applications is driving the development of wireless sensor node technology towards a monolithic system-on-a-chip implementation. Of particular interest are hostile environment scenarios where radiation and thermal extremes exist. Radiation hardening by design has been recogn...2009
20 Mastrangelo, Carlos H.Characterization of electrical interferences for ground reaction sensor clusterThis paper presents the characterization of electrical interferences for a high-resolution error-correcting biomechanical ground reaction sensor cluster (GRSC), developed for improving inertial measurement unit (IMU) position sensing accuracy. The GRSC is composed of 13 x 13 sensing nodes, which can...2012-01-01
21 Mastrangelo, Carlos H.; Young, Darrin J.Low-interference sensing electronics for high-resolution error-correcting biomechanical ground reaction sensor clusterAbstract- This paper presents a low-interference and low -power sensing electronics design for a high-resolution errorcorrecting biomechanical ground reaction sensor cluster (GRSC) developed for improving inertial measurement unit (IMU) positioning resolution and accuracy. The GRSC is composed of 13...2010
22 Tasdizen, Tolga; Jones, Bryan W.; Whitaker, Ross T.; Marc, Robert E.Ultrastructural mapping of neural circuitry: a computational frameworkComplete mapping of neuronal networks requires data acquisition at synaptic resolution with canonical coverage of tissues and robust neuronal classification. Transmission electron microscopy (TEM) remains the optimal tool for network mapping. However, capturing high resolution, large, serial sectio...2009
23 Myers, Chris J.Timed circuits: a new paradigm for high-speed designAbstract| In order to continue to produce circuits of increasing speeds, designers must consider aggressive circuit design styles such as self-resetting or delayed-reset domino circuits used in IBM's gigahertz processor (GUTS) and asynchronous circuits used in Intel's RAPPID instruction length de...2001
24 Stevens, KennethInterfacing synchronous and asynchronous domains for open core protocolIntellectual property (IP) blocks are connected in a system on chip using a bus or network-on-chip (NoC). IP reuse is facilitated by the modularity that results when using common interfaces between the IP cores and the bus or NoC. This paper investigates and implements several versions of one of the...2014-01-01
25 Myers, Chris J.; Stevens, KennethAn asynchronous instruction length decoderAbstract-This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocessor architecture. A prototype complex instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolvi...2001
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