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TitleDateType
1 Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device2013-01-01Text
2 Non-uniform power access in large caches with low-swing wires2009Text
3 Simon II kernel reference manual1986Text
4 Reducing the complexity of the register file in dynamic superscalar processors2001Text
5 Precise garbage collection for C2009-01-01Text
6 Towards scalable, energy-efficient, bus-based on-chip networks2010Text
7 Static and dynamic structure in design patterns2001-11-01Text
8 Fast stereoscopic images with ray-traced volume rendering1994Text
9 Data distributed, parallel algorithm for ray-traced volume rendering1993Text
10 Low latency self-timed flow-through FIFOs1995Text
11 Graphical man/machine communications: December 19711971-12Text
12 Reduced latency self-timed FIFO circuits1994Text
13 Data distributed, parallel algorithm for ray-traced volume rendering1993Text
14 Interactive isosurface ray tracing of time-varying tetrahedral volumes2007-11Text
15 Estimating performance of an ray- tracing ASIC design2006Text
16 Dynamic memory hierarchy performance optimization2000Text
17 Dynamically allocating processor resources between nearby and distant ILP2001Text
18 Distributed interactive ray tracing for large volume visualization2003Text
19 Higher-order image statistics for unsupervised, information-theoretic, adaptive, image filtering2005-04-15Text
20 Interactive ray tracing of arbitrary implicits with SIMD interval arithmetic2007-09Text
21 Some unusual micropipeline circuits1993Text
22 Evolving real-time systems using hierarchical scheduling and concurrency analysis2003-01-01Text
23 Staged reads: mitigating the impact of DRAM writes on DRAM reads2012-01-01Text
24 Parallel volume rendering using binary-swap compositing1994Text
25 Approximate Bregman near neighbors in sublinear time: beyond the triangle inequality2012-01-01Text
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