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26 - 50 of 111
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TitleDateTypeSetname
26 Dynamically tuning processor resources with adaptive processing2003-12Textir_uspace
27 High level optimizations in compiling process descriptions to asynchronous circuits1992Textir_uspace
28 A fast parallel squarer based on divide-and-conquer1995Textir_uspace
29 Timing constraints for high speed counterflow-clocked pipelining1995Textir_uspace
30 Performance analysis and optimization of asynchronous circuits1994Textir_uspace
31 Structured, technology independent VLSI design1989Textir_uspace
32 Low latency self-timed flow-through FIFOs1995Textir_uspace
33 HOP: A formal model for synchronous circuits using communicating fundamental mode symbolic automata1992Textir_uspace
34 The NSR processor1993Textir_uspace
35 Self-timed design in GaAs - case study of a high-speed parallel multiplier1996Textir_uspace
36 Reduced latency self-timed FIFO circuits1994Textir_uspace
37 ACT: A DFT tool for self-timed circuits1997Textir_uspace
38 Practical advances in asynchronous design and in asynchronous/synchronous interfaces1999Textir_uspace
39 Case studies in symbolic model checking1994Textir_uspace
40 Practical advances in asynchronous design1997Textir_uspace
41 Some recent asynchronous system design methodologies1990Textir_uspace
42 Efficient symbolic simulation based verification using the parametric form of boolean expressions (rev.)1991Textir_uspace
43 Editorial asynchronous architecture1996-01-01Textir_uspace
44 Performance analysis and optimization of asynchronous circuits1994Textir_uspace
45 The NSR processor prototype1992Textir_uspace
46 Peephole optimization of asynchronous networks through process composition and burst-mode machine generation1993Textir_uspace
47 Dataflow computers: a tutorial and survey1980Textir_uspace
48 Simulation of Cells1984Textir_uspace
49 Identifying sources of opinions with conditional random fields and extraction patterns2005Textir_uspace
50 Re-visiting the performance impact of microarchitectural floorplanning2006Textir_uspace
26 - 50 of 111