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Title
Date
Type
1
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device
2013-01-01
Text
2
Non-uniform power access in large caches with low-swing wires
2009
Text
3
Simon II kernel reference manual
1986
Text
4
Reducing the complexity of the register file in dynamic superscalar processors
2001
Text
5
Precise garbage collection for C
2009-01-01
Text
6
Towards scalable, energy-efficient, bus-based on-chip networks
2010
Text
7
Static and dynamic structure in design patterns
2001-11-01
Text
8
Fast stereoscopic images with ray-traced volume rendering
1994
Text
9
Data distributed, parallel algorithm for ray-traced volume rendering
1993
Text
10
Low latency self-timed flow-through FIFOs
1995
Text
11
Graphical man/machine communications: December 1971
1971-12
Text
12
Reduced latency self-timed FIFO circuits
1994
Text
13
Data distributed, parallel algorithm for ray-traced volume rendering
1993
Text
14
Interactive isosurface ray tracing of time-varying tetrahedral volumes
2007-11
Text
15
Estimating performance of an ray- tracing ASIC design
2006
Text
16
Dynamic memory hierarchy performance optimization
2000
Text
17
Dynamically allocating processor resources between nearby and distant ILP
2001
Text
18
Distributed interactive ray tracing for large volume visualization
2003
Text
19
Higher-order image statistics for unsupervised, information-theoretic, adaptive, image filtering
2005-04-15
Text
20
Interactive ray tracing of arbitrary implicits with SIMD interval arithmetic
2007-09
Text
21
Some unusual micropipeline circuits
1993
Text
22
Evolving real-time systems using hierarchical scheduling and concurrency analysis
2003-01-01
Text
23
Staged reads: mitigating the impact of DRAM writes on DRAM reads
2012-01-01
Text
24
Parallel volume rendering using binary-swap compositing
1994
Text
25
Approximate Bregman near neighbors in sublinear time: beyond the triangle inequality
2012-01-01
Text
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