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CreatorTitleDescriptionSubjectDate
1 Michell, NickPPL 1.2mu gallium arsenide cell setThe purpose of this note is to describe the 1.2/i gallium arsenide PPL cell set - not only what is included, but design decisions made along the way. The first section is an overview of the Umitations imposed by the use of gallium arsenide technology, the next section describes the trade-offs in des...Gallium arsenide cells; PPL cell set1993
2 Carter, Tony M.Path-programmable logicPath-Programmable Logic (PPL) is a structured IC design methodology under development at the University of Utah. PPL employs a sea-of-wires approach to design. In PPL, design is done entirely using cells for both functionality and interconnect. PPL cells may have modifiers that change either their ...Path-Programmable Logic; PPL1989
3 Jacobson, HansRealizing burstmode circuits via STG speed independent synthesisThis report discusses the similarities and differences of STG and Burstmode specifications and synthesis methods. The first part of the report examines the applicability and efficiency of STG's single controller fork-join concurrency ability versus Burstmode's partitioned fork-join concurrency appr...Burstmode circuits; STG1997
4 Brunvand, Erik L.Automatic rapid prototyping of semi-custom VLSI circuits using actel FPGAsAbstract : We describe a technique for translating semi-custom VLSI circuits automatically into field programmable gate arrays (FPGAs) for rapid prototyping to develop a system. Using an array multiplier as an example of this translation, the VLSI circuits are designed using a cell-matrix based envi...1995
5 Smith, Kent F.Automatic rapid prototyping of semi-custom VLSI circuits using FPGAsWe describe a technique for translating semi-custom VLSI circuits automatically, integrating two design environments, into field programmable gate arrays (FPGAs) for rapid and inexpensive prototyping. The VLSI circuits are designed using a cell-matrix based environment that produces chips with densi...Semi-custom; VLSI circuits1994
6 Davis, Alan L.Data driven nets: a maximally concurrent, procedural, parallel process representation for distributed control systemsA procedural parallel process representation, known as data-driven nets is described. The sequencing mechanism of the data-driven representation is based on the principle of data dependency. Operations are driven into action by the arrival of the required working set of input operands. Execution of ...Data driven nets1978
7 Jacobson, HansDesign and validation of a simultaneous multi-threaded DLX processorModern day computer systems rely on two forms of parallelism to achieve high performance, parallelism between individual instructions of a program (ILP) and parallelism between individual threads (TLP). Superscalar processors exploit ILP by issuing several instructions per clock, and multiprocessors...DLX processor; Validation1999
8 Gopalakrishnan, GaneshSome unusual micropipeline circuitsWe present a few unusual Micropipelines (Sutherland, CACM, September 1989) that employ the Muller C-ELEMENT or an extension of the C-ELEMENT called LOCKC (Liebchen and Gopalakrishnan, ICCD, 1992). We first describe two variations of the two-dimensional Micropipeline structure realized using ordinary...Micropipeline circuits; Micropipelines1993
9 Starkey, MikeA lisp-based occam interpreterThe OCCAM programming language is an implementation of Communicating Sequential Processes and is used in a number of different areas. These areas usually require explicitly describing small-grain paralleslism. OCCAM programs formed by such descriptions can be tested for correctness by executing the...Lisp-based; Occam interpreter1991
10 Brunvand, Erik L.Peephole optimization of asynchronous macromodule networksAbstract- Most high-level synthesis tools for asynchronous circuits take descriptions in concurrent hardware description languages and generate networks of macromodules or handshake components. In this paper, we propose a peephole optimizer for these networks. Our peephole optimizer first deduces an...1999
11 Michell, NickA gallium arsenide mutual exclusion elementA mutual exclusion element is a key component in building asynchronous and self-timed circuits. As part of our effort to design high performance self-timed circuits, we have designed a mutual exclusion element in gallium arsenide. This circuit has been fabricated in a 1.2? process and tested. A test...Mutual exclusion element; Self-timed circuits1993
12 Brunvand, Erik L.Using FPGAs to prototype a self-timed floating point co-processorSelf- timed circuits offer advantages over their synchronously clocked counterparts in a number of situations. However, self-timed design techniques are not widely used at present for a variety of reasons. One reason for the lack of experimentation with self-timed systems is the lack of commercially...1994
13 Brunvand, Erik L. ; Gopalakrishnan, GaneshHigh-level asynchronous system design using the ACK frameworkDesigning asynchronous circuits is becoming easier as a number of design styles are making the transition from research projects to real, usable tools. However, designing asynchronous "systems" is still a difficult problem. We define asynchronous systems to be medium to large digital systems whose...2000
14 Brunvand, Erik L.A partial scan methodology for testing self-timed circuitsThis paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other proposed test methods for self-timed circuits, this technique offers better fault coverage than methods using self-checking techniques, and re...Self-timed circuits; Testing1995
15 Brunvand, Erik L.A partial scan methodology for testing self-timed circuitsThis paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other proposed test methods for self-timed circuits, this technique offers better fault coverage than methods using self-checking techniques, and ...1995
16 Jacobson, Hans; Gopalakrishnan, GaneshApplication specific asynchronous microengines for efficient high-level controlDespite the growing interest in asynchronous circuits programmable asynchronous controllers based on the idea of microprogramming have not been actively pursued Since programmable control is widely used in many commercial ASICs to allow late correction of design errors to easily upgrade product f...Asynchronous microengines1997
17 Brunvand, Erik L.Testing self-timed circuits using partial scanThis paper presents a partial scan method for testing both the control and data path parts of macromodule based self-timed circuits for stuck-at faults. Compared with other proposed test methods for testing control paths in self-timed circuits, this technique offers better fault coverage under a st...1995
18 Davis, AlAn introduction to asynchronous circuit designThe purpose of this monograph is to provide both an introduction to field of asynchronous digital circuit design and an overview of the practical state of the art in 1997. In the early days of digital circuit design, little distinction was made between synchronous and asynchronous circuits. However,...Asynchronous circuit design1997
19 Brunvand, Erik L.Peephole optimization of asynchronous macromodule networksMost high level synthesis tools for asynchronous circuits take descriptions in concurrent hardware description languages and generate networks of macromodules or handshake components. In this paper we describe a peephole optimizer for such macromodule networks that often effects area and/or time im...1994
20 Jacobson, HansApplication specific asynchronous microgengines for efficient high-level controlDespite the growing interest in asynchronous circuits, programmable asynchronous controllers based on the idea of microprogramming have not been actively pursued. Since programmable control is widely used in many commercial ASICs to allow late correction of design errors, to easily upgrade product ...Asynchronous microgengines; Programmable asynchronous controllers1997
21 Brunvand, Erik L.Critical hazard free test generation for asynchronous circuitsWe describe a technique to generate critical hazard-free tests for self-timed control circuits build using a macromodule library, in a partial scan based DFT environment. We propose a 6 valued algebra to generate these tests which are guaranteed to be critical hazard free under an unbounded delay m...1997
22 Smith, Kent F.PPL quick reference guide (CMOS)This work was supported in part by Defense Research Projects Agency under Contract Number DAAK1184K0017. All opinions, findings, conclusions or recommendations expressed in this document are those of the author(s) and do not necessarily reflect the view of DARPA.CMOS1987
23 Brunvand, Erik L.DFT for fast testing of self-timed control circuitsIn this paper, we present a methodology to perform fast testing of the control path of self-timed circuits [91]. The speedup is achieved by testing all the execution paths in the control simultaneously. The circuits considered in this paper are those designed using an OCCAM based circuit compile...1995
24 Riloff, Ellen M.Recognizing and organizing opinions expressed in the world pressTomorrow's question answering systems will need to have the ability to process information about beliefs, opinions, and evaluations-the perspective of an agent. Answers to many simple factual questions-even yes/no questions-are affected by the perspective of the information source. For example...Opinions; Opinion recognition; World press; MPQA project; Multiple perspectives2003
25 Balasubramonian, RajeevDynamically tuning processor resources with adaptive processingUsing adaptive processing to dynamically tune major microprocessor resources, developers can achieve greater energy efficiency with reasonable hardware and software overhead while avoiding undue performance loss.Adaptive processing; Energy efficiency; DRI-cache2003-12
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