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Creator | Title | Description | Subject | Date |
76 |
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Brunvand, Erik L.; Gopalakrishnan, Ganesh; Hurdle, John Franklin | Reliable interface design for combining asynchronous and synchronous circuits | Abstract: In order to successfully integrate asynchronous and synchronous designs, great care must be taken at the interface between the two types of systems. Synchronizing asynchronous inputs with a free running clock can cause well-known problems with metastability in the synchronization circuits... | | 1993 |
77 |
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Organick, Elliott I. | Transformation of Ada program units into silicon (Fourth Semiannual technical report 83 Apr 1 - 83 Nov 15) | This report, augmented with several appended papers and supplementary reports describes the most recent six months of work on the research project, "Transformation of Ada Programs into Silicon". This report is also the last of the series to be rendered under the current contact. | Transformation; Ada program units; Silicon | 1983 |
78 |
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Fujimoto, Richard M. | Optimal performance of distributed simulation programs | This paper describes a technique to analyze the potential speedup of distributed simulation programs. A distributed simulation strategy is proposed which minimizes execution time through the use of an oracle to control the simulation. Because the strategy relies on an oracle, it cannot be used for ... | Distributed simulation programs | 1987 |
79 |
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Brunvand, Erik L. | Testing micropipelines | Micropipelines, self-timed event-driven pipelines, are an attractive way of structuring asynchronous systems that exhibit many of the advantages of general asynchronous systems, but enough structure to make the design of significant systems practical. As with any design method, testing is critical. ... | | 1994 |
80 |
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Carter, John B. | Design of a parallel vector access unit for SDRAM memory systems | Parallel Vector Access is a technique that exploits the regularity of vector or stream accesses to perform them efficiently in parallel on a multi-bank memory system. The performance of applications that have vector accesses may be improved using a memory controller that performs scatter/gather oper... | Parallel vector access; SDRAM memory; Multi-bank memory system | 1999 |
81 |
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Henderson, Thomas C. | An O(n) time discrete relaxation architecture for real-time processing of the consistent labeling problem | Discrete relaxation techniques have proven useful in solving a wide range of problems in digital signal and digital image processing, artificial intelligence, operations research, and machine vision. Much work has been devoted to finding efficient hardware architectures. This paper shows that a conv... | Discrete relaxation techniques | 1986 |
82 |
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Gopalakrishnan, Ganesh | Hierarchical action refinement: a methodology for compiling asynchronous circuits from a concurrent HDL | A hardware specification formalism called hopCP is introduced, hopCP provides an uniform notation t o describe the causal relationships between a set of nonatomic actions which capture the computational, concurrency, control and communication aspects of hardware behavior. A systematic approach to sy... | Hierarchical action refinement; Hardware specification formalism; hopCP | 1991 |
83 |
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Akella, Venkatesh | hopCP: language definition, semantics and examples | We describe a formalism for high level modeling of hardware based on flow graphs and nonatomic actions called hopCP. A module is the description of a hardware system in hopCP, which contains a flow graph to model the behavioral aspects and ports which represent the communication links. Operations ar... | hopCP | 1990 |
84 |
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Richardson, William F. | Fred: an architecture for a self-timed decoupled computer | Decoupled computer architectures provide an effective means of exploiting instruction level parallelism. Self-timed micropipeline systems are inherently decoupled due to the elastic nature of the basic FIFO structure, and may be ideally suited for constructing decoupled computer architectures. Fred ... | Decoupled computer; Fred | 1995 |
85 |
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Akella, Venkatesh | Testing two-phase transition signaling based self-timed circuits in a synthesis environment | The problem of testing self-timed circuits generated by an automatic synthesis system is studied. Two-phase transition signalling is assumed and the circuits are targetted for an asynchronous macromodule based implementation as in [?, ?, ?, ?]. The partitioning of the circuits into control blocks, ... | Testing; two-phase; transition signaling; self-timed circuits | 1993 |
86 |
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Mathew, Binu K.; Davis, Al; Fang, Zhen | A Gaussian probability accelerator for SPHINX 3 | Accurate real-time speech recognition is not currently possible in the mobile embedded space where the need for natural voice interfaces is clearly important. The continuous nature of speech recognition coupled with an inherently large working set creates significant cache interference with other... | Speech recognition; SPHINX 3; Speech recognizers | 2003-07-22 |
87 |
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Bhanu, Bir | Shape matching of two-dimensional objects | In this paper we present results in the areas of shape matching of nonoccluded and occluded two-dimensional objects. Shape matching is viewed as a "segment matching" problem. Unlike the previous work, the technique is based on a stochastic labeling procedure which explicitly maximizes a criterion ... | Shape matching; Two-dimensional objects; Segment matching | 1984 |
88 |
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Gerpheide, George E. | Bit-driven logic: a style of digital logic for VLSI design | This memo describes a new style of low-level digital logic design called Bit-Driven Logic (BDL) which may prove attractive for the design of VLSI chips. BDL is an application of speed-independent, data-flow ideas to a very low level. It has the advantages of good locality, clockless operation, and... | Bit-Driven Logic; BDL; Digital logic design; VLSI chips | 1980 |
89 |
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Gopalakrishnan, Ganesh | HOP: a process model for synchronous hardware semantics, and experiments in process composition | We present a language "Hardware viewed as Objects and Processes" (HOP) for specifying the structure, behavior, and timing of hardware systems. HOP embodies a simple process model for lock-step synchronous processes. An absproc specification written in HOP describes the externally observable behavior... | HOP; Synchronous hardware semantics | 1988 |
90 |
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Balasubramonian, Rajeev | Non-uniform power access in large caches with low-swing wires | Modern processors dedicate more than half their chip area to large L2 and L3 caches and these caches contribute significantly to the total processor power. A large cache is typically split into multiple banks and these banks are either connected through a bus (uniform cache access - UCA) or an on-c... | Large caches; Low-swing wires; Non Uniform Cache Access; NUCA | 2009 |
91 |
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Stoller, Leigh B. | PPE-level protocols for carpet clusters | We describe the lowest level of a suite of protocols for workstation cluster multicomputers: the parts implemented in hardware by a Protocol Processing Engine (PPE) and the software level immediately above the PPE. The stated goal of this work is extremely low end-to-end latency communications on in... | Workstation clusters; Protocol Processing Engine; PPE | 1994 |
92 |
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Grodstein, Joel | User's manual for the sisyphus simulation environment | This report describes how to create and simulate a design with Sisyphus. Inasmuch as Sisyphus is written in Symbolics-Lisp, some familiarity with both Lisp and with Symbolics computers is presumed. In addition, the concepts presented here presume an acquaintance with [3]. First, a disclaimer ? this... | Sisyphus; Simulation environment; Symbolics-Lisp; Symbolics computers | 1986 |
93 |
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Sobh, Tarek M.; Henderson, Thomas C. | Robot manipulator prototyping (Complete Design Review) | Prototyping is an important activity in engineering. Prototype development is a good test for checking the viability of a proposed system. Prototypes can also help in determining system parameters, ranges, or in designing better systems. The interaction between several modules (e.g., S/W, VLSI, CAD,... | Robot manipulator; Prototyping | 1994 |
94 |
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Organick, Elliott I. | CASL - A language for automating the implementation of computer architectures | The computer Architecture Specification Language (CASL), described in this paper, is intended for use by computer architects CASL is a state machine description language especially useful for describing digital systems at the "register transfer" level and designed to meet the needs of the computer a... | Computer Architecture Specification Language | 1979 |
95 |
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Balasubramonian, Rajeev | Power efficient resource scaling in partitioned architectures through dynamic heterogeneity | The ever increasing demand for high clock speeds and the desire to exploit abundant transistor budgets have resulted in alarming increases in processor power dissipation. Partitioned (or clustered) architectures have been proposed in recent years to address scalability concerns in future billion-tr... | Partitioned architectures; Clustered architectures; Energy × Delay2, Temperature; Dynamic frequency scaling; Thermal emergency | 2006 |
96 |
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Gu, Jun | Fast structured design of VLSI circuits | We believe that a structured, user-friendly, cost-effective tool for rapid implementation of VLSI circuits which encourages students to participate directly in research projects are the key components in digital integrated circuit (IC) education. In this paper, we introduce our VLSI education activ... | VLSI circuits; Rapid implementation | 1988 |
97 |
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Balasubramonian, Rajeev | Integrating adaptive on-chip storage structures for reduced dynamic power | Energy efficiency in microarchitectures has become a necessity. Significant dynamic energy savings can be realized for adaptive storage structures such as caches, issue queues, and register files by disabling unnecessary storage resources. Prior studies have analyzed individual structures and their... | Microarchitecture | 2002 |
98 |
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Carter, Tony M. | The path programmable logic (PPL) user's manual | This manual describes the primitive NMOS path programmable logic cells currently in use at the University of Utah. It contains detailed descriptions, schematics and composite layout of all cells. Also included are PPL programming rules as well as layout design rules for each cell set. | | 1982 |
99 |
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Hoogenboom, Peter J. | Semantic definition of a subset of the structured query language (SQL) | SQL is a relational database definition and manipulation language. Portions of the manipulation language are readily described in terms of relational algebra. The semantics of a subset of the SQL select statement is described. The select statement allows the user to query the database. The select st... | | 1991 |
100 |
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Balasubramonian, Rajeev | Staged reads: mitigating the impact of DRAM writes on DRAM reads | Main memory latencies have always been a concern for system performance. Given that reads are on the criti- cal path for CPU progress, reads must be prioritized over writes. However, writes must be eventually processed and they often delay pending reads. In fact, a single channel in the main memory ... | | 2012-01-01 |