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CreatorTitleDescriptionSubjectDate
51 Brunvand, Erik L.Speed without fear: composable self-timed GaAs circuitsWe have designed a set of self-timed gallium arsenide building blocks that are suitable for composing into larger systems. Systems designed using these modules can be easier to design and modify than their globally clocked counterparts, while maintaining high performance. The modules are suitable ...Gallium arsenide circuits; Self-timed1993
52 Carter, Tony M.ASSASSIN : a CAD system for self-timed control-unit designMany software systems exist for automatically implementing synchronous state machines . Presented is this paper is a software system -- ASSASSIN -- for the design and automatic layout of self-timed (or speed- independent) control units as integrated circuit modules.ASSASSIN; Self-timed control units1982
53 Smith, Kent F.PPL quick reference guide (NMOS)This work was supported in part by Defense Research Projects Agency under Contract Number DAAK1184K0017. All opinions, findings, conclusions or recommendations expressed in this document are those of the author(s) and do not necessarily reflect the view of DARPA.NMOS1986
54 Soares, Marshall A.SOAR user's manualAbstract: The development of simulation and test stimulus and checking of circuits with that stimulus is the source or many circuit bugs. The SOAR conversion package is a C library that generates the stimuli for gate-level simulation, circuit simulation and integrated circuit test The conversion pa...SOAR; Conversion package; C library; Simulation1997
55 Brunvand, Erik L.Self-timed design with dynamic domino circuitsWe introduce a simple hierarchical design technique for building high-performance self-timed components using dynamic domino-style circuits. This technique is useful for building handshaking style functional blocks and for self-timed data path components. We wrap the dynamic domino circuit in a wra...2003
56 Gopalakrishnan, Ganeshpsolve: Deciding satisfiability for presburger formulae using automata, rewriting and a model checkerPresburger formulas are an expressive but decidable language of arithmetic expressions and boolaen connectives with quantification. psolve is a prototype of an automata based tool for deciding the satisfiability of Presburger formulae extended with a predicate that recognizes powers of two. The uniq...psolve; Presburger formulas; Satisfiability; Automata; Rewriting; Model checker1999
57 Sobh, Tarek M.A survey on sensor classifications for industrial applicationsThe importance of sensors in industrial applications is a result of the introduction of many robotics, automation, and intelligent control techniques into factory floors. Research and improvements need to be continuously performed to meet the challenges in automation and manufacturing applications i...Sensor classifications; Industrial applications; Sensors1995
58 Gopalakrishnan, GaneshA transformational approach to asynchronous high-level synthesisAsynchronous high-level synthesis is aimed at transforming high level descriptions of algorithms into efficient asynchronous circuit implementations. This approach is attractive from the point of view of the flexibility it affords in performing high level program transformations on users' initial d...High level synthesis tool; SHILPA1993
59 Smith, Kent F.PPL design examples (NMOS30 Version)This work was supported in part by Defense Advanced Research Projects Agency under Contract number DAAK1184K0017. All opinions, findings, conclusions or recommendations expressed in this document are those of the author(s) and do not necessarily reflect the views of DARPA.Circuits; Design1986
60 Balasubramonian, RajeevLeveraging 3D technology for improved reliabilityAggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower supply voltages have increased the vulnerability of computer systems towards transient faults. An increase in within-die an...Reliability; Redundant multi-threading, 3D die-stacking; Parameter variation; Soft errors; Dynamic timing errors; Power-efficient microarchitecture; On-chip temperature2007-12
61 Organick, Elliott I.; Lindstrom, Gary E.Transforming an Ada program unit to silicon and verifying its behavior in an Ada environment: a first experimentMicroelectronics technology has advanced so rapidly and been so successful that we are new having to build large systems with a multitude of diverse, interacting components. Some components of these systems exhibit distinct architectures and may, in fact, be implemented following different choices o...Transformation; Ada program units; Silicon1983
62 Riesenfeld, Richard F.Computer aided designThe report is based on the proposal submitted to the National Science Foundation in September 1981, as part of the Coordinated Experimental Computer Science Research Program. The sections covering the budget and biographical data on the senior research personnel have not been included. Also, the sec...1984
63 Gopalakrishnan, GaneshDynamic reordering of high latency transactions in time-warp simulation using a modified micropipelineTime warp based simulation of discrete-event systems is an efficient way to overcome the synchronization overhead during distributed simulation. As computations may proceed beyond synchronization barriers in time warp, multiple checkpoints of state need to be maintained to be able to rollback inva...Asynchronous design; Micropipelines; Dynamic instruction reordering; Time warp simulations1992
64 Gopalakrishnan, GaneshDesign and verification of the rollback chip using HOP: a case study of formal methods applied to hardware designThe use of formal methods in hardware design improves the quality of designs in many ways: it promotes better understanding of the design; it permits systematic design refinement through the discovery of invariants; and it allows design verification (informal or formal). In this paper we illustrate ...Rollback chip; Verification; HOP; Hardware design; RBC1990
65 Richardson, William F.; Brunvand, Erik L.The NSR processor prototypeThe NSR (Non-Synchronous RISC) processor is a general purpose processor structured as a collection of self-timed units that operate concurrently and communicate over bundled data channels in the style of micropipelines. These units correspond to standard synchronous pipeline stages such as Instructi...Self-timed Systems; Asynchronous systems; Micropipelines; FPGAs; RISC processor; NSR1992
66 Balasubramonian, RajeevOptimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, and thermal management strategies. There are a number of interconnect design considerations that influence power/performanc...CACTI 6.0; Non-uniform cache architectures (NUCA); Cache models; Memory hierarchies; On-chip interconnects2007-12
67 Gopalakrishnan, GaneshFrom process-oriented functional specifications to efficient asynchronous circuitsA methodology for high-level synthesis and performance optimization of asynchronous circuits is described. A specification language called hopCP which is based on a simple extension to classical flow graphs is introduced. The extension involves the addition of expression actions to a flow graph, to ...Synthesis; Performance optimization1991
68 Brunvand, Erik L.Self-timed circuits using DCVSL semi-bundled delay wrappersWe present a technique for generating robust self-timed completion signals for general dynamic datapath circuits. The wrapper circuit is based on our previous domino semi-bundled delay (SBD) circuits, but uses DCVSL circuits in the wrapper for higher performance. We describe the basic SBD-DCVSL...2005
69 Brunvand, Erik L.HDL modeling for analysis and optimization of asynchronous controllersWe propose a simulation-based technique for analysis and optimization of extended burst-mode (XBM) asynchronous controllers. In asynchronous controllers of this sort, timing information on control signals is significant both for performance enhancement and timing validation. Timing information, ...2005
70 Brunvand, Erik L.Translating concurrent programs into delay-insensitive circuitsPrograms written in a subset of occam are automatically translated into delay-insensitive circuits using syntax-directed techniques. The resulting circuits are improved using semantics-preserving circuit-to-circuit transformations. Since each step of the translation process can be proven correct, th...1989
71 Stoller, Leigh B.Low latency workstation cluster communications using sender-based protocolsThe use of workstations on a local area network to form scalable multicomputers has become quite common. A serious performance bottleneck in such "carpet clusters" is the communication protocol that is used to send data between nodes. We report on the design and implementation of a class of communic...Workstations; Scalable multicomputers; Sender-based; Communication protocols1996
72 Kessler, Robert R.Visual threads: the benefits of multithreading in visual programming languagesAfter working with the CWave visual programming language, we discovered that many of our target domains required the ability to define parallel computations within a program. CWave has a strongly hierarchical model of computation, so it seemed like adding the ability to take a part of the hierarchy ...Visual threads; multithreading; CWave1997
73 Riloff, Ellen M.Corpus-based identification of non-anaphoric noun phrasesCoreference resolution involves finding antecedents for anaphoric discourse entities, such as definite noun phrases. But many definite noun phrases are not anaphoric because their meaning can be understood from general world knowledge (e.g., "the White House" or "the news media"). We have develope...Corpus-based identification; Non-anaphoric noun phrases; Coreference resolution; MUC-4; Discourse entity; DE1999
74 Carter, Tony M.Cascade: hardware for high/variable precision arithmeticThe Cascade hardware architecture for high/variable precision arithmetic is described. It uses a radix-16 redundant signed-digit number representation and directly supports single or multiple precision addition, subtraction, multiplication, division, extraction of the square root and computation...1989
75 Riloff, Ellen M.Corpus-based bootstrapping algorithm for semi-automated semantic lexicon constructionMany applications need a lexicon that represents semantic information but acquiring lexical information is time consuming. We present a corpus-based bootstrapping algorithm that assists users in creating domain-specifi c semantic lexicons quickly. Our algorithm uses a representative text corpus for ...Bootstrapping algorithm; Lexicon construction1999-06
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