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CreatorTitleDescriptionSubjectDate
26 Gopalakrishnan, GaneshHigh level optimizations in compiling process descriptions to asynchronous circuitsAsynchronous/'Self-Timed designs are beginning to attract attention as promising means of dealing with the complexity of modern VLSI technology. In this paper, we present our views on why asynchronous systems matter. We then present details of our high level synthesis tool SHILPA that can automatic...Self-timed; VLSI1992
27 Smith, Kent F.A fast parallel squarer based on divide-and-conquerFast and small squarers are needed in many applications such as image compression. A new family of high performance parallel squarers based on the divide-and-conquer method is reported. Our main result was realizing the basis cases of the divide-and-conquer recursion by using optimized n-bit primiti...Squarer; Parallel squarers; Divide-and-conquer; MOPS; CMOS1995
28 Gopalakrishnan, GaneshTiming constraints for high speed counterflow-clocked pipeliningWith the escalation of clock frequencies and the increasing ratio of wire- to gate-delays, clock skew is a major problem to be overcome in tomorrow's high-speed VLSI chips. Also, with an increasing number of stages switching simultaneously comes the problem of higher peak power consumption. In our ...Timing constraints; clock frequencies; clock skew; high-speed; VLSI chips; counterflow-clocked pipelining1995
29 Gopalakrishnan, GaneshPerformance analysis and optimization of asynchronous circuitsAsynchronous/Self-timed circuits are beginning to attract renewed attention as promising means of dealing with the complexity of modern VLSI designs. However, there are very few analysis techniques or tools available for estimating the performance of asynchronous circuits. In this paper we adapt th...Asynchronous circuits; Performance analysis; Optimization; VLSI circuits1994
30 Gu, JunStructured, technology independent VLSI designRapid advancement in new semiconductor technologies has created a need for the design of existing integrated circuits using these new technologies. These new technologies are required to provide improved performance, smaller feature sizes and lower costs. The conversion of an integrated circuit fro...VLSI design; semiconductor technologies1989
31 Brunvand, Erik L.Low latency self-timed flow-through FIFOsSelf-timed flow-through FIFOs are constructed easily using only a single C-element as control for each stage of the FIFO. Throughput can be very high in this type of FIFO as the communication required to send new data to the FIFO is local to only the first element of the FIFO. Circuit density can ...1995
32 Gopalakrishnan, GaneshHOP: A formal model for synchronous circuits using communicating fundamental mode symbolic automataWe study synchronous digital circuits in an abstract setting. A circuit is viewed as a collection of modules connected through their boundary ports, where each port assumes a fixed direction (input or output) over one cycle of operation, and can change directions across cycles. No distinction is ma...HOP1992
33 Brunvand, Erik L.The NSR processorThe NSR (Non-Synchronous RISC) processor is a general-purpose computer structured (IS U collection of self-timed blocks that operate concurrently and communicate over bundled data channels in the style of micropipelines [3, 16]. These blocks correspond to standard synchronous pipeline stages such ...1993
34 Brunvand, Erik L.; Smith, Kent F.Self-timed design in GaAs - case study of a high-speed parallel multiplierAbstract-The problems with synchronous designs at high clock frequencies have been well documented. This makes an asynchronous approach attractive for high speed technologies like GaAs. We investigate the issues involved by describing the design of a parallel multiplier that can be part of a floati...1996
35 Brunvand, Erik L.Reduced latency self-timed FIFO circuitsSelf-timed flow-through FIFOs are constructed easily using only a single C-element as control for each stage of the FIFO. Throughput can be very high in FIFOs of this type because new data can be sent to the FIFO after communicating locally with only the first element of the FIFO. Therefore the thro...FIFO circuits; Self-timed; Flow-through; Reduced latency1994
36 Brunvand, Erik L.ACT: A DFT tool for self-timed circuitsThis paper presents a Design for Testability (DFT) tool called ACT (Asynchronous Circuit Testing) which uses a partial scan technique to make macro-module based selftimed circuits testable. The ACT tool is the first oFits kind for testing macro-module based self-timed circuits. ACT modifies design...1997
37 Brunvand, Erik L.Practical advances in asynchronous design and in asynchronous/synchronous interfacesAsynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practical asynchronous circuit and system design in four areas: controllers, datapaths, processors, and the design of asynchr...1999
38 Gopalakrishnan, GaneshCase studies in symbolic model checkingThe need to formally verify hardware and software systems before they are deployed the real world has been recognized for several decades now. This is especially true of concurrent systems that are even more difficult to debug than sequential systems. For example, many of the protocols that get emp...Symbolic model checking; Hardware verification; Software verification1994
39 Brunvand, Erik L.Practical advances in asynchronous designRecent practical advances in asynchronous circuit and system design have resulted in renewed interest by circuit designers. Asynchronous systems are being viewed as in increasingly viable alternative to globally synchronous system organization. This tutorial will present the current state of the art...1997
40 Gopalakrishnan, GaneshSome recent asynchronous system design methodologiesWe present an in-depth study of some techniques for asynchronous system design, analysis, and verification. After defining basic terminology, we take one simple example - a four-phase t o two-phase converter - and present its design using (a) classical flow-tables; (b) Signal Transition Graphs of [...Asynchronous system design1990
41 Gopalakrishnan, GaneshEfficient symbolic simulation based verification using the parametric form of boolean expressions (rev.)We present several new techniques to make symbolic simulation based verification efficient. These techniques hinge on the use of the parametric form of a boolean expression (e.g. the parametric form for the boolean expression XQ V -<xi is the equivalent expression 3a b . (XQ = a V 6) A (xi = b), whe...Symbolic simulation; Verification1991
42 Brunvand, Erik L.Editorial asynchronous architectureAsynchronous design is enjoying a worldwide resurgence of interest following several decades in obscurity. Many of the early computers employed asynchronous design techniques, but since the mid 1970s almost all digital design has been based around the use of a central clock. The clock simplifies mos...1996-01-01
43 Brunvand, Erik L.Performance analysis and optimization of asynchronous circuitsAsynchronous/Self-timed circuits are beginning to attract renewed attention as promising means of dealing with the complexity of modern VZSI designs. Very few analysis techniques or tools are available for estimating their performance. In this paper we adapt the theory of Generalized Timed Petri-n...1994
44 Richardson, William F.; Brunvand, Erik L.The NSR processor prototypeThe NSR Non Synchronous RISC processor is a general purpose processor structured as a collection of self timed units that operate concurrently and communicate over bundled data channels in the style of micropipelines?? These units correspond to standard synchronous pipeline stages such as Instr...Self-timed Systems; Asynchronous systems; Micropipelines; FPGAs; RISC processor1992
45 Gopalakrishnan, GaneshPeephole optimization of asynchronous networks through process composition and burst-mode machine generationIn this paper we discuss the problem of improving the e ciency of macromodule networks generated through asynchronous high level synthesis We compose the behaviors of the modules in the sub network being optimized using Dill s trace theoretic operators to get a single behavioral description for ...Macromodule networks; Peephole; Asynchronous networks1993
46 Davis, A.L.Dataflow computers: a tutorial and surveyThe demand for very high performance computer has encouraged some researchers in the computer science field to consider alternatives to the conventional notions of program and computer organization. The dataflow computer is one attempt to form a new collection of consistent systems ideas to improve ...Dataflow computers1980
47 Pickett, Forrest B.Simulation of CellsA self-timed cell set and library for the design of integrated circuits is presented. The cell set and library are two different cellular methods of designing integrated circuits. These have been incorporated to form a hybrid system which exploits the advantages provided by each. The cell set an...Self-timed; Cell set1984
48 Riloff, Ellen M.Identifying sources of opinions with conditional random fields and extraction patternsRecent systems have been developed for sentiment classification, opinion recognition, and opinion analysis (e.g., detecting polarity and strength). We pursue another aspect of opinion analysis: identifying the sources of opinions, emotions, and sentiments. We view this problem as an information ext...Sentiment classification; Opinion recognition; Opinion analysis; Conditional random fields; AutoSlog; Sources of opinions2005
49 Balasubramonian, RajeevRe-visiting the performance impact of microarchitectural floorplanningThe placement of microarchitectural blocks on a die can significantly impact operating temperature. A floorplan that is optimized for low temperature can negatively impact performance by introducing wire delays between critical pipeline stages. In this paper, we identify subsets of wire delays tha...Microarchitectural floorplanning; Wire delays; Floorplanning algorithms; Microprocessor operating temperature; Critical loops; Pipelines2006
50 Gopalakrishnan, GaneshPeephole optimization of asynchronous networks through process composition and burst-mode machine generationIn this paper, we discuss the problem of improving the efficiency of macromodule networks generated through asynchronous high level synthesis. We compose the behaviors of the modules in the sub-network being optimized using Dill's trace-theoretic operators to get a single behavioral description for ...Peephole optimization; Macromodule networks; Process composition; Burst-mode1993
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