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Balasubramonian, Rajeev | Dynamically tunable memory hierarchy | The widespread use of repeaters in long wires creates the possibility of dynamically sizing regular on-chip structures. We present a tunable cache and translation lookaside buffer (TLB) hierarchy that leverages repeater insertion to dynamically trade off size for speed and power consumption on a per... | Microarchitecture; High performance microprocessors; Reconfigurable architectures; Energy and performance of on-chip caches; Translation lookaside buffer (TLB); Tunable cache | 2003-10 |
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