Filters: Department: "Computing, School of" School Or College: "College of Engineering" Collection: "ir_uspace"
| Creator | Title | Description | Subject | Date | ||
|---|---|---|---|---|---|---|
| 251 |
 |
Shirley, Peter S. | Direct Ray tracing of smoothed and displacement mapped triangles | We present an algorithm for ray tracing displacement maps that requires no additional storage over the base model. Displacement maps are rarely used in ray tracing due to the cost associated with storing and intersecting the displaced geometry. This is unfortunate because displacement maps allow the... | Ray tracing displacement maps | 2000 |
| 252 |
 |
Riesenfeld, Richard F. | Discrete B-splines and subdivision techniques in compter-aided geometric design and computer graphics | The relevant theory of discrete 5-sphnes with associated new algorithms is extended to provide a framework for understanding and implementing general subdivision schemes for nonuniform B-splines. The new derived polygon corresponding to an arbitrary refinement of the knot vector for an existing .B-... | 1979 | |
| 253 |
 |
Sobh, Tarek M. | Discrete event control for inspection and reverse engineering | We address the problem of intelligent sensing in this work. In particular, we use discrete event dynamic systems (DEDS) to guide the sensing of mechanical parts for industrial inspection and reverse engineering. | Discrete event control; Intelligent sensing; Inspection; Discrete event dynamic systems; DEDS | 1994 |
| 254 |
 |
Evans, David | Display of complex three dimensional finite element models | Complex three dimensional models can be displayed after an automatic generation of a finite element (panel) mapping. although this automatic generation algorithm fails at certain levels of model complexity, the elimination of these failures can be accomplished through user interaction. This report p... | Three dimensional models; Finite element models | 1978 |
| 255 |
 |
Peterson, John W. | Distributed computation for computer animation | Computer animation is a very computationally intensive task. Recent developments in image synthesis, such as shadows, reflections and motion blur enhance the quality of computer animation, but also dramatically increase the amount of CPU time needed to do it. Fortunately, the computations involved w... | Distributed computation | 1987 |
| 256 |
 |
Parker, Steven G.; Hansen, Charles D. | Distributed interactive ray tracing for large volume visualization | We have constructed a distributed parallel ray tracing system that interactively produces isosurface renderings from large data sets on a cluster of commodity PCs. The program was derived from the SCI Institute's interactive ray tracer (*-Ray), which utilizes small to large shared memory platforms, ... | Ray tracing; Volume rendering; Large data; Cluster computing; Distributed shared memory | 2003 |
| 257 |
 |
Thompson, William B.; Willemsen, Peter; Gooch, Amy A.; Creem-Regehr, Sarah Hope | Does the quality of the computer graphics matter when judging distances in visually immersive environments? | In the real world, people are quite accurate judging distances to locations in the environment, at least for targets resting on the ground plane and distances out to about 20m. Distance judgments in visually immersive environments are much less accurate. Several studies have now shown that in vis... | Visually immersive environments | 2002-12-05 |
| 258 |
 |
Riloff, Ellen M. | Domain-specific coreference resolution with lexicalized features | Most coreference resolvers rely heavily on string matching, syntactic properties, and semantic attributes of words, but they lack the ability to make decisions based on individual words. In this paper, we explore the benefits of lexicalized features in the setting of domain-specific coreference reso... | 2014-01-01 | |
| 259 |
 |
Evans, John | DPOS programming manual | This manual describes the basic concepts of the DPOS Metalanguage and the programming language DPOS Scheme. | DPOS; Programming manual | 1990 |
| 260 |
 |
Kessler, Robert R. | DPOS: A metalanguage and programming environment for parallel processors | The complexity and diversity of parallel programming languages and computer architectures hinders programmers in developing programs and greatly limits program portability. All MIMD parallel programming systems, however, address common requirements for process creation, process management, and inte... | DPOS; MIMD parallel programming | 1990 |
| 261 |
 |
Lepreau, Jay | DRAFT: work in progress - - - comments solicited evolving Mach 3.0 to use migrating threads | Like most operating systems, Mach 3.0 views threads as statically associated with a single task. An alternative model is that of migrating threads, in which a single thread abstraction moves between tasks with the logical flow of control, and "server" code is passively executed. We have compatibly r... | DRAFT | 1993 |
| 262 |
 |
Regehr, John | Dynamic CPU management for real-time, middleware-based systems | Many real-world distributed, real-time, embedded (DRE) systems, such as multi-agent military applications, are built using commercially available operating systems, middleware, and collections of pre-existing software. The complexity of these systems makes it difficult to ensure that they maintain h... | 2004-01-01 | |
| 263 |
 |
Eide, Eric Norman; Regehr, John; Lepreau, Jay | Dynamic CPU management for real-time, middleware-based systems | Many real-world distributed, real-time, embedded (DRE) systems, such as multi-agent military applications, are built using commercially available operating systems, middleware, and collections of pre-existing software. The complexity of these systems makes it difficult to ensure that they maintai... | CPU management | 2004-01-30 |
| 264 |
 |
Balasubramonian, Rajeev | Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches | In future multi-cores, large amounts of delay and power will be spent accessing data in large L2/L3 caches. It has been recently shown that OS-based page coloring allows a non-uniform cache architecture (NUCA) to provide low latencies and not be hindered by complex data search mechanisms. In this ... | Page coloring; Shadow-memory addresses; Cache capacity allocation; Data/page migration; Last level caches; Non-uniform cache architectures (NUCA) | 2009-02 |
| 265 |
 |
Balasubramonian, Rajeev | Dynamic memory hierarchy performance optimization | Although microprocessor performance continues to increase at a rapid pace, the growing processor-memory speed gap threatens to limit future performance gains. In this paper, we propose a novel configurable cache and TLB as an alternative to conventional two-level hierarchies. This organization le... | Microprocessor performance; Processor-memory speed gap | 2000 |
| 266 |
 |
Orr, Douglas B.; Mecklenburg, Robert; Hoogenboom, Peter J.; Lepreau, Jay | Dynamic program monitoring and transformation using the OMOS object server | In traditional monolithic operating systems the con?? straints of working within the kernel have limited the sophistication of the schemes used to manage exe?? cutable program images By implementing an exe?? cutable image loader as a persistent user??space pro?? gram we can extend system prog... | Program monitoring; OMOS object server | 1992 |
| 267 |
 |
Orr, Douglas B. | Dynamic program monitoring and transformation using the OMOS object server | In traditional monolithic operating systems the constraints of working within the kernel have limited the sophistication of the schemes used to manage executable program images. By implementing an executable image loader as a persistent user-space program, we can extend system program loading capabi... | Program monitoring; Object/Meta-Object Server; OMOS | 1992 |
| 268 |
 |
Gopalakrishnan, Ganesh | Dynamic reordering of high latency transactions in time-warp simulation using a modified micropipeline | Time warp based simulation of discrete-event systems is an efficient way to overcome the synchronization overhead during distributed simulation. As computations may proceed beyond synchronization barriers in time warp, multiple checkpoints of state need to be maintained to be able to rollback inva... | Asynchronous design; Micropipelines; Dynamic instruction reordering; Time warp simulations | 1992 |
| 269 |
 |
Bargteil, Adam Wade | Dynamic sprites | Traditional methods for creating dynamic objects and characters from static drawings involve careful tweaking of animation curves and/or simulation parameters. Sprite sheets offer a more drawing-centric solution, but they do not encode timing information or the logic that determines how objects shou... | 2014-01-01 | |
| 270 |
|
Bargteil, Adam Wade | Dynamic sprites | Traditional methods for creating dynamic objects and characters from static drawings involve careful tweaking of animation curves and/or simulation parameters. Sprite sheets offer a more drawing-centric solution, but they do not encode timing information or the logic that determines how objects shou... | 2013-01-01 | |
| 271 |
 |
Balasubramonian, Rajeev | Dynamically allocating processor resources between nearby and distant ILP | Modern superscalar processors use wide instruction issue widths and out-of-order execution in order to increase instruction-level parallelism (ILP). Because instructions must be committed in order so as to guarantee precise exceptions, increasing ILP implies increasing the sizes of structures s... | Instruction-level parallelism; Microarchitecture; Primary thread; Future thread; Instruction reuse buffer | 2001 |
| 272 |
 |
Balasubramonian, Rajeev | Dynamically managing the communication-parallelism trade-off in future clustered processors | Clustered microarchitectures are an attractive alternative to large monolithic superscalar designs due to their potential for higher clock rates in the face of increasingly wire-delay-constrained process technologies. As increasing transistor counts allow an increase in the number of clusters, th... | Clustered architectures; Microarchitecture; Decentralized cache; Interconnects | 2003 |
| 273 |
 |
Balasubramonian, Rajeev | Dynamically tunable memory hierarchy | The widespread use of repeaters in long wires creates the possibility of dynamically sizing regular on-chip structures. We present a tunable cache and translation lookaside buffer (TLB) hierarchy that leverages repeater insertion to dynamically trade off size for speed and power consumption on a per... | Microarchitecture; High performance microprocessors; Reconfigurable architectures; Energy and performance of on-chip caches; Translation lookaside buffer (TLB); Tunable cache | 2003-10 |
| 274 |
 |
Balasubramonian, Rajeev | Dynamically tuning processor resources with adaptive processing | Using adaptive processing to dynamically tune major microprocessor resources, developers can achieve greater energy efficiency with reasonable hardware and software overhead while avoiding undue performance loss. | Adaptive processing; Energy efficiency; DRI-cache | 2003-12 |
| 275 |
 |
Regehr, John | Edicts: implementing features with flexible binding times | In a software product line, the binding time of a feature is the time at which one decides to include or exclude a feature from a product. Typical binding site implementations are intended to support a single binding time only, e.g., compile time or run time. Sometimes, however, a product line must... | 2008-01-01 |