Technical reports, manuscripts and photographs document the early history of the University of Utah Computer Science Department.
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The A3000: An asynchronous version of the R3000 | This thesis presents the architectural design and implementation of an N-stage Self-Timed RISC processor based on a subset of the MIPS R3000. The goal is to lay the ground work to show it will be possible in the future to build an asynchoronous pipelined RISC processor that has the chance to to comm... | A3000; asynchronous; computers | 1995-03 |
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