Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Computing, School of |
Creator |
Balasubramonian, Rajeev |
Other Author |
Muralimanohar, Naveen; Ramani, Karthik |
Title |
Power efficient resource scaling in partitioned architectures through dynamic heterogeneity |
Date |
2006 |
Description |
The ever increasing demand for high clock speeds and the desire to exploit abundant transistor budgets have resulted in alarming increases in processor power dissipation. Partitioned (or clustered) architectures have been proposed in recent years to address scalability concerns in future billion-transistor microprocessors. Our analysis shows that increasing processor resources in a clustered architecture results in a linear increase in power consumption, while providing diminishing improvements in single-thread performance. To preserve high performance to power ratios, we claim that the power consumption of additional resources should be in proportion to the performance improvements they yield. Hence, in this paper, we propose the implementation of heterogeneous clusters that have varying delay and power characteristics. A cluster's performance and power characteristic is tuned by scaling its frequency and novel policies dynamically assign frequencies to clusters, while attempting to either meet a fixed power budget or minimize a metric such as Energy×Delay2 (ED2). By increasing resources in a power-efficient manner, we observe a 11% improvement in ED2 and a 22.4% average reduction in peak temperature, when compared to a processor with homogeneous units. Our proposed processor model also provides strategies to handle thermal emergencies that have a relatively low impact on performance. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
First Page |
100 |
Last Page |
111 |
DOI |
10.1109/ISPASS.2006.1620794 |
Subject |
Partitioned architectures; Clustered architectures; Energy × Delay2, Temperature; Dynamic frequency scaling; Thermal emergency |
Subject LCSH |
Computer architecture; Microprocessors; Microprocessors -- Energy consumption |
Language |
eng |
Conference Title |
2006 IEEE International Symposium on Performance Analysis of Systems and Software; March 19-21, 2006; Austin, TX, USA |
Bibliographic Citation |
Muralimanohar, N., Ramani, K., & Balasubramonian, R. (2006). Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. ISPASS 2006: IEEE International Symposium on Performance Analysis of Systems and Software, 1620794, 100-11. |
Rights Management |
(c) 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. http://dx.doi.org/10.1109/ISPASS.2006.1620794 |
Format Medium |
application/pdf |
Format Extent |
256,051 bytes |
Identifier |
ir-main,11477 |
ARK |
ark:/87278/s6hd8dbs |
Setname |
ir_uspace |
ID |
707158 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6hd8dbs |