Hierarchical action refinement: a methodology for compiling asynchronous circuits from a concurrent HDL

A hardware specification formalism called hopCP is introduced, hopCP provides an uniform notation t o describe the causal relationships between a set of nonatomic actions which capture the computational, concurrency, control and communication aspects of hardware behavior. A systematic approach to synthesize asynchronous circuits from hopCP, based on hierarchical action refinement, is presented. Actions in hopCP could denote control, value communication, and computation (e.g.: evaluation of functional expressions). The salient features of our scheme include systematic resource allocation and control decomposition with the ability to use standard off the shelf components and the flexibility to retarget the compilation to different data transfer protocols and hardware primitives. The synthesis of LRU (least recently used) circuit used in the design of cache memory and virtual memory systems is presented to illustrate our ideas.