Leveraging wire properties at the microarchitecture level

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Publication Type Journal Article
School or College College of Engineering
Department Computing, School of
Creator Balasubramonian, Rajeev
Other Author Muralimanohar, Naveen; Ramani, Karthik; Cheng, Liqun; Carter, John B.
Title Leveraging wire properties at the microarchitecture level
Date 2006-11
Description In future microprocessors, communication will emerge as a major bottleneck. The authors advocate composing future interconnects of some wires that minimize latency, some that maximize bandwidth, and some that minimize power. A microarchitecture aware of these wire characteristics can steer on-chip data transfers tot he most appropriate wires, thus improving performance and saving energy.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
Journal Title IEEE Micro
Volume 26
Issue 6
First Page 40
Last Page 52
DOI 10.1109/MM.2006.123
citatation_issn 0272-1732
Subject Microarchitecture; Interconnects; Cache coherence
Subject LCSH Computer architecture; Microprogramming; Microprocessors; Electric wiring; Cache memory; Microprocessors -- Energy consumption
Language eng
Bibliographic Citation Balasubramonian, R., Muralimanohar, N., Ramani, K., Cheng, L., & Carter, J. B. (2006). Leveraging wire properties at the microarchitecture level. IEEE Micro, 26(6), 40-52.
Rights Management (c) 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. http://dx.doi.org/10.1109/MM.2006.123
Format Medium application/pdf
Format Extent 186,831 bytes
Identifier ir-main,11478
ARK ark:/87278/s6543659
Setname ir_uspace
ID 706388
Reference URL https://collections.lib.utah.edu/ark:/87278/s6543659
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