| Publication Type |
journal article |
| School or College |
College of Engineering |
| Department |
Electrical & Computer Engineering |
| Creator |
Myers, Chris J. |
| Other Author |
Thacker, Robert A. |
| Title |
Synthesis of timed circuits using BDDs* |
| Date |
1997 |
| Description |
This paper presents a tool which synthesizes timed circuits from reduced state graphs. Using timing information to reduce state graphs can lead to significantly smaller and faster circuits. The tool uses implicit techniques (binary decision diagrams) to represent these graphs. This allows us to synthesize larger, more complex systems which may be intractable with an explicit representation. We are also able to create a parameterized family of solutions, facilitating technology mapping. |
| Type |
Text |
| Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
| First Page |
1 |
| Last Page |
4 |
| Language |
eng |
| Bibliographic Citation |
Thacker, R. A., & Myers, C. J. (1997). Synthesis of timed circuits using BDDs. International Workshop on Logic Synthesis, 1-4. May. |
| Rights Management |
(c) 1997 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
| Format Medium |
application/pdf |
| Format Extent |
66,075 bytes |
| Identifier |
ir-main,15051 |
| ARK |
ark:/87278/s6xh08pb |
| Setname |
ir_uspace |
| ID |
706207 |
| Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6xh08pb |
