A fast parallel squarer based on divide-and-conquer

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Publication Type Journal Article
School or College College of Engineering
Department Computing, School of
Creator Smith, Kent F.
Other Author Yoo, Jae-tack; Gopalakrishnan, Ganesh
Title A fast parallel squarer based on divide-and-conquer
Date 1995
Description Fast and small squarers are needed in many applications such as image compression. A new family of high performance parallel squarers based on the divide-and-conquer method is reported. Our main result was realizing the basis cases of the divide-and-conquer recursion by using optimized n-bit primitive squarers, where n is in the range of 2 to 6. This method reduced the gate count and provided shorter critical paths. A chip implementing an 8-bit squarer was designed, fabricated and successfully tested, resulting in 24 MOPS using a 2-p CMOS fabrication technology. This squarer had two additional features: increased number of squaring operations per unit circuit area, and the potential for reduced power consumption per squaring operation.
Type Text
Publisher University of Utah
First Page 1
Last Page 7
Subject Squarer; Parallel squarers; Divide-and-conquer; MOPS; CMOS
Language eng
Bibliographic Citation Yoo, J.-t., Smith, K. F., & Gopalakrishnan, G. (1995). A fast parallel squarer based on divide-and-conquer. 1-7. UUCS-95-011.
Series University of Utah Computer Science Technical Report
Relation is Part of ARPANET
Rights Management ©University of Utah
Format Medium application/pdf
Format Extent 1,643,674 bytes
Identifier ir-main,16206
ARK ark:/87278/s64q8cgv
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2015-04-22
ID 705888
Reference URL https://collections.lib.utah.edu/ark:/87278/s64q8cgv
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