Publication Type |
journal article |
School or College |
College of Engineering |
Department |
Electrical & Computer Engineering |
Creator |
Myers, Chris J. |
Other Author |
Belluomini, Wendy; Killpack, Kip; Mercer, Eric; Peskin, Eric; Zheng, Hao |
Title |
Timed circuits: a new paradigm for high-speed design |
Date |
2001 |
Description |
Abstract| In order to continue to produce circuits of increasing speeds, designers must consider aggressive circuit design styles such as self-resetting or delayed-reset domino circuits used in IBM's gigahertz processor (GUTS) and asynchronous circuits used in Intel's RAPPID instruction length decoder. These new timed circuit styles, however, cannot be efficiently and accurately analyzed using traditional static timing analysis methods. This lack of efficient analysis tools is one of the reasons for the lack of mainstream acceptance of these design styles. This paper discusses several industrial timed circuits and gives an overview of our timed circuit design methodology. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
Language |
eng |
Bibliographic Citation |
Myers, C., Belluomini, W., Killpack, K., Mercer, E., Peskin, E., & Zheng, H. (2001). Timed circuits: a new paradigm for high-speed design. Asia and South Pacific Design Automation Conference. February. |
Rights Management |
(c) 2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
212,660 bytes |
Identifier |
ir-main,15035 |
ARK |
ark:/87278/s6cj8z02 |
Setname |
ir_uspace |
ID |
705834 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6cj8z02 |