A partial scan methodology for testing self-timed circuits

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Publication Type technical report
School or College College of Engineering
Department Computing, School of
Creator Brunvand, Erik L.
Other Author Khoche, Ajay
Title A partial scan methodology for testing self-timed circuits
Date 1995
Description This paper presents a partial scan method for testing control sections of macromodule based self-timed circuits for stuck-at faults. In comparison with other proposed test methods for self-timed circuits, this technique offers better fault coverage than methods using self-checking techniques, and requires fewer storage elements to be made scannable than full scan approaches with similar fault coverage. A new method is proposed to test the sequential network in this partial scan environment. Experimental data is presented to show that high fault coverage is possible using this method with only a subset of storage elements being made scannable.
Type Text
Publisher University of Utah
Subject Self-timed circuits; Testing
Language eng
Bibliographic Citation Khoche, A., & Brunvand, E. L. (1995). A partial scan methodology for testing self-timed circuits. UUCS-95-001.
Series University of Utah Computer Science Technical Report
Relation is Part of ARPANET
Rights Management ©University of Utah
Format Medium application/pdf
Format Extent 3,622,302 bytes
Identifier ir-main,16197
ARK ark:/87278/s62r4939
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2021-05-06
ID 705523
Reference URL https://collections.lib.utah.edu/ark:/87278/s62r4939