The 'Test model-checking' approach to the verification of formal memory models of multiprocessors

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Publication Type technical report
School or College College of Engineering
Department Computing, School of
Creator Gopalakrishnan, Ganesh
Other Author Nalumansu, Ratan; Ghughal, Rajnish; Mokkedem, Abdel
Title The 'Test model-checking' approach to the verification of formal memory models of multiprocessors
Date 1998
Description We offer a solution to the problem of verifying formal memory models of processors by combining the strengths of model-checking and a formal testing procedure for parallel machines. We characterize the formal basis for abstracting the tests into test automata and associated memory rule safety properties whose violations pinpoint the ordering rule being violated. Our experimental results on Verilog models of a commercial split transaction bus demonstrates the ability of our method to effectively debug design models during early stages of their development.
Type Text
Publisher University of Utah
Subject Test Model-checking; Formal memory; Verification
Subject LCSH Multiprocessors
Language eng
Bibliographic Citation Nalumansu, R., Ghughal, R., Mokkedem, A. & Gopalakrishnan, G. (1998). The 'Test model-checking' approach to the verification of formal memory models of multiprocessors. UUCS-98-008.
Series University of Utah Computer Science Technical Report
Relation is Part of ARPANET
Rights Management ©University of Utah
Format Medium application/pdf
Format Extent 3,800,398 bytes
Identifier ir-main,15921
ARK ark:/87278/s6mp5mp9
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2015-04-24
ID 705511
Reference URL https://collections.lib.utah.edu/ark:/87278/s6mp5mp9
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