Low-power integrated circuit for a wireless 100-electrode neural recording system

In the past decade, neuroscientists and clinicians have begun to use implantable MEMS multielectrode arrays (e.g., [1]) to observe the simultaneous activity of many neurons in the brain. By observing the action potentials, or "spikes," of many neurons in a localized region of the brain it is possible to gather enough information to predict hand trajectories in real time during reaching tasks [2]. Recent experiments have shown that it is possible to develop neuroprosthetic devices - machines controlled directly by thoughts - if the activity of multiple neurons can be observed.

ISSCC 2006 / SESSION 30 / SILICON FOR BIOLOGY / 30.2 30.2 A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System Reid Harrison, Paul Watkins, Ryan Kier, Robert Lovejoy, Daniel Black, Richard Normann, Florian Solzbacher University of Utah, Salt Lake City, UT In the past decade, neuroscientists and clinicians have begun to use implantable MEMS multielectrode arrays (e.g., 111) to observe the simultaneous activity of many neurons in the brain. By observing the action potentials, or "spikes," of many neurons in a localized region of the brain it is possible to gather enough information to predict hand trajectories in real time during reaching tasks 121. Recent experiments have shown that it is pos­sible to develop neuroprosthetic devices - machines controlled directly by thoughts - if the activity of multiple neurons can be observed. Currently, data is recorded from implanted multielectrode arrays using bundles of fine wires and head-mounted connectors; all electronics for amplification and recording is external to the body. This presents three major barriers to the development of practi­cal neuroprosthetic devices: (1) the transcutaneous connector pro­vides a path for infection, (2) external noise and interfering sig­nals easily couple to the wires conveying weak neural signals (<500nV) from high-impedance electrodes (>100kQ), and (3) the connector and external electronics are typically large and bulky compared to the -5mm electrode arrays. To eliminate these prob­lems, data from the implanted electrodes should be transmitted out of the body wirelessly. This requires electronics at the record­ing site to amplify, condition, and digitize the neural signals from each electrode. These circuits must be powered wirelessly since rechargeable batteries are relatively large and have limited life­times. Low power operation (clOOmW) is essential for any implanted electronics as elevated temperatures can easily kill neurons. A wireless, fully-implantable neural recording system is being developed to facilitate neuroscience research and neuroprosthet­ic applications (see Fig. 30.2.1). The system is based on the Utah Microelectrode Array (UEA), a 10x10 array of platinum-tipped silicon extracellular electrodes 111. This paper describes the development of a mixed-signal integrated circuit that will be flip- chip bonded to the back of the UEA using Au/Sn reflow soldering. This chip will directly connect to all 100 electrodes, amplify the neural signals from each electrode, digitize this data, and trans­mit it over an RF link (see Fig. 30.2.2). Power will be delivered to a 6mm coil mounted on the back of the chip using an inductive link. (This coil is under development; the chip is currently test­ed using dc power for initial tests and a 19mm coil for wireless power tests.) The entire device will be coated in parylene and sil­icon carbide to protect it from internal body fluids. The integrated circuit measures 4.7x5.9mm2 and was fabricated in a commercial O.S^im 3M2P CMOS process (see Fig. 30.2.7). An on-chip bridge rectifier and bandgap-referenced low-dropout volt­age regulator provides a 3.3V dc power supply from a 2.64MHz ac coil power signal. External capacitors are used to resonate with the power coil and smooth the unregulated dc supply. A system clock is recovered from the coil frequency, and ASK modulation of the power signal allows the external user to send commands and configuration data to the chip at 6.5 kb/s (see [31 for a similar power/data link). The center of the chip consists of a 10x10 array of amplifiers laid out in a 400[im pitch, corresponding to the inter-electrode spacing. A bond pad local to each amplifier allows direct connection of the chip to the UEA. Twelve of the 100 plat­inum- tipped electrodes are used as "ground" or "reference" elec­trodes; the remaining 88 electrodes are connected to integrated low-noise neural signal amplifiers. The amplifiers are ac-coupled to eliminate the large dc offset found at the electrode-tissue inter­face; their bandwidth extends from l-5kHz to pass neural spikes and reject low-frequency local field potentials (see Fig. 30.2.3). The amplifiers have a measured gain of 60dB and input-referred noise of S.luVrms. Each amplifier draws only 12.8nA of supply current; we use the design techniques presented in |4| to mini­mize noise and power consumption. Individual amplifiers may be powered down with a command signal so that unused electrode channels do not dissipate power. A 9b charge-redistribution ADC is used to digitize the signal from one amplifier at 15kSamples/s. The ADC consumes less than 30nA, and has measured INL and DNL <0.8 LSB for all but the lowest 50 codes. Digitizing all 88 neural waveforms simultane­ously would generate prohibitively high data rates (>10Mb/s) for low-power RF transmission. Therefore, we perform on-site data reduction by incorporating one-bit "spike detector" comparators into each amplifier block. The spike detection threshold is set by a 7b DAC. The user selects the detection threshold level and also controls an analog MUX that routes the desired electrode ampli­fier signal to the ADC. The chip produces a 330 kb/s data stream that interleaves ADC data from one selected amplifier, spike detector data from all amplifiers, and parity bits. Figure 30.2.4 shows recorded neural data (courtesy of K. Shenoy, Stanford University) played through a neural amplifier on the chip; either the complete digitized waveform or simply the detected spikes may be transmitted. (An alternate approach to neural data reduction is presented in [51.) Digitized neural data is transmitted using a fully-integrated 433MHz FSK transmitter. The VCO uses a planar spiral induc­tor (54nH, Q ~ 3) optimized for maximum LC. parallel-circuit equivalent resistance to minimize power consumption (see Fig. 30.2.7). The inductor also serves as a transmitting antenna. At an operating supply current of 1.9mA, we are able to receive FSK- modulated data (at -86dBm) at a distance of 13cm using a half­wave resonant dipole antenna (see Fig. 30.2.5). The complete chip dissipates 13.5mW of power when the unregu­lated dc voltage is at its minimum allowable level of 3.55V. The FSK transmitter consumes 50% of this power, and the low-noise neural signal amplifiers consume 30% with all amplifiers pow­ered up. The transmitter power could be reduced by using a process with a thick-metal option to increase inductor Q, The measured performance of the integrated neural interface chip is summarized in Fig. 30.2.6. References: [1J C.T. Nordhausen, E.M. Maynard, and R.A. Normann, "Single Unit Recording Capabilities of a 100-Microeleclrode Array," Brain Ses., 726: 129-140, 1996. [2J J. Wessberg, el al., ""Real-Time Prediction of Hand Trajectory by Ensembles of Cortical Neurons in Primates," Nature, vol. 408: 361-365, 2000. [3J H. Yu and K. Najafi, "Low-Power Interface Circuits for Bio-Implantable Microsystems," ISSCC Dig. Tech. Papers, pp. 194-195, Feb., 2003. [4J R.R. Harrison and C. Charles, "A Low-Power, Low-Noise CMOS Amplifier for Neural Recording Applications," IEEE J. Solid State Circuits, vol. 38, no. 6, pp. 958-965, June, 2003. [5J R. Olsson and K. Wise, "A Three-Dimensional Neural Recording Microsystem with Implantable Data Compression Circuitry," ISSCC Dig. Tech. Papers, pp. 558-559, Feb., 2005. • 2 0 0 6 IEEE I n t e r n a t io n a l S o l i d - S t a t e C ir c u i t s C o n f e r e n c e 1 - 4 2 4 4 - 0 0 7 9 - 1 / 0 6 © 2 0 0 6 IEEE Authorized licensed use limited to: The University of Utah. Downloaded on May 17,2010 at 22:16:21 UTC from IEEE Xplore. Restrictions apply. ISSCC 2006 / February 8, 2006 / 2:00 PM Power receiving coil (Au) on polyimide with ceramic ferrite backing Integrated circuit with neural amplifiers, signal processing, and RF telemetry electronics SMD Capacitor (0402 package) i i i i i i i i i i i i i i i i i 1.2 mm H 400 pm pitch Utah Microelectrode Entire assembly coated in parylene and silicon carbide Array Bulk micromachined silicon with platinum tips and glass isolation between shanks Figure 30.2.1: Complete Integrated Neural Interface (INI) assembly. 6-mm power/data receiving coil r------------------------------------------------------ (2.64 MHz ASK) on chip 500-pm data transmit coil (433 MHz FSK) Figure 30.2.2: Integrated Neural Interface system block diagram. Amplifier Output [mV] Digitized Waveform Vref Stage 1 Amplifier Gain: 100 Bandwidth: 1 kHz to 5 kHz High-Pass Filter Gain: 1 Cutoff Freq: 1 kHz Stage 2 Amplifier Gain: 10 Bandwidth: 5 kHz Figure 30.2.3: Schematic of neural signal amplifier. Resistors are made from high-resistance polysilicon. Figure 30.2.4: Response of wireless-powered chip to neural waveform played from waveform generator: analog output of a neural signal amplifier (top), waveform reconstructed from ADC output (middle), output of corresponding spike detector (bottom). Figure 30.2.5: Spectrum of FSK data transmitter sending a typical data frame at 330kb/s. Dipole antenna was positioned 13cm from chip. Integrated Neural Interface IC Measured Performance Power/command signal frequency 2.64 MHz Minimum required receive coil voltage amplitude 5.7 V(peak) 3.3-V voltage regulator dropout (II = 3 mA) 250 mV Load regulation (Il = 2-10 mA) 0.15 % Line regulation (Vunreo = 3.5 V - 8.0 V) <0.30 %/V Maximum command input data rate (ASK) 6.5 kbps Number of Channels/Electrodes 88 signal, 12 ground Neural Signal Amplifier Gain 60.1 dB (1.1 -5 kHz) Input Referred Noise 5.1 pVrms Individual Amplifier Supply Current 12.8 pA ADC resolution (LSB = 2.4 pV electrode referred) 9 bits ADC sampling rate 15.0 kSamples/s ADC INL/DNL error (codes 50-511) ±0.8 LSB/ ±0.6 LSB Spike detector threshold resolution (LSB = 4.8 pV electrode referred) 7 bits FSK data transmission frequency 433 MHz FSK data rate 330 kbps Received signal power at distance of 13 cm -86 dBm Total chip power dissipation 13.5 mW Total chip area (0.5-pm, 2P3M CMOS) 27.3 mm2 Figure 30.2.6: Table summarizing measured INI chip performance. V • 2 0 0 6 IEEE I n t e r n a t io n a l S o l i d - S t a t e C ir c u i t s C o n f e r e n c e 1 - 4 2 4 4 - 0 0 7 9 - 1 / 0 6 © 2 0 0 6 IEEE Authorized licensed use limited to: The University of Utah. Downloaded on May 17,2010 at 22:16:21 UTC from IEEE Xplore. Restrictions apply. ISSCC 2006 / SESSION 30 / SILICON FOR BIOLOGY / 30.2 Figure 30.2.7: Dis photo of 4.7x5.9mm2 integrated neural interface chip. Insets show FSK data transmitter with integrated 54 nH inductor (left) and neural amplifier/spike detector cell (right). • 2 0 0 6 IEEE I n t e r n a t io n a l S o l i d - S t a t e C ir c u i t s C o n f e r e n c e 1 - 4 2 4 4 - 0 0 7 9 - 1 / 0 6 © 2 0 0 6 IEEE Authorized licensed use limited to: The University of Utah. Downloaded on May 17,2010 at 22:16:21 UTC from IEEE Xplore. Restrictions apply. ISSCC 2006 / SESSION 30 / SILICON FOR BIOLOGY / 30.2 Power receiving coil (Au) on polyimide with ceramic ferrite backing Integrated circuit with neural amplifiers, signal processing, and RF telemetry electronics SMD Capacitor (0402 package) H 400 pm pitch Entire assembly coated in parylene and silicon carbide Utah Microelectrode Bulk micromachined silicon with platinum tips and glass isolation between shanks Figure 30.2.1: Complete Integrated Neural Interface (INI) assembly. • 2 0 0 6 IEEE I n t e r n a t io n a l S o l i d - S t a t e C ir c u i t s C o n f e r e n c e 1 - 4 2 4 4 - 0 0 7 9 - 1 / 0 6 © 2 0 0 6 IEEE Authorized licensed use limited to: The University of Utah. Downloaded on May 17,2010 at 22:16:21 UTC from IEEE Xplore. Restrictions apply. ISSCC 2006 / SESSION 30 / SILICON FOR BIOLOGY / 30.2 Figure 30.2.2: Integrated Neural Interface system block diagram. • 2 0 0 6 IEEE I n t e r n a t io n a l S o l i d - S t a t e C ir c u i t s C o n f e r e n c e 1 - 4 2 4 4 - 0 0 7 9 - 1 / 0 6 © 2 0 0 6 IEEE Authorized licensed use limited to: The University of Utah. Downloaded on May 17,2010 at 22:16:21 UTC from IEEE Xplore. Restrictions apply. ISSCC 2006 / SESSION 30 / SILICON FOR BIOLOGY / 30.2 Stage 1 Amplifier Gain: 100 Bandwidth: 1 kHz to 5 kHz A. Y High-Pass Filter Gain: 1 Cutoff Freq: 1 kHz j Y Stage 2 Amplifier Gain: 10 Bandwidth: 5 kHz Figure 30.2.3: Schematic of neural signal amplifier. Resistors are made from high-resistance polysilicon. • 2 0 0 6 IEEE I n t e r n a t io n a l S o l i d - S t a t e C ir c u i t s C o n f e r e n c e 1 - 4 2 4 4 - 0 0 7 9 - 1 / 0 6 © 2 0 0 6 IEEE Authorized licensed use limited to: The University of Utah. Downloaded on May 17,2010 at 22:16:21 UTC from IEEE Xplore. Restrictions apply. ISSCC 2006 / SESSION 30 / SILICON FOR BIOLOGY / 30.2 Figure 30.2.4: Response of wireless-powered chip to neural waveform played from waveform generator: analog output of a neural signal amplifier (top), waveform reconstructed from ADC output (middle), output of corresponding spike detector (bottom). • 2 0 0 6 IEEE I n t e r n a t io n a l S o l i d - S t a t e C ir c u i t s C o n f e r e n c e 1 - 4 2 4 4 - 0 0 7 9 - 1 / 0 6 © 2 0 0 6 IEEE Authorized licensed use limited to: The University of Utah. Downloaded on May 17,2010 at 22:16:21 UTC from IEEE Xplore. Restrictions apply. ISSCC 2006 / SESSION 30 / SILICON FOR BIOLOGY / 30.2 84 ■IQA -------------------1--------------------1-------------------1--------------------1-------------------1--------------------1-------------------1-------------------- 432.2 432.4 432.6 432.8 433 433.2 433.4 433.6 433.8 frequency [MHz] Figure 30.2.5: Spectrum of FSK data transmitter sending a typical data frame at 330kb/s. Dipole antenna was positioned 13cm from chip. • 2 0 0 6 IEEE I n t e r n a t io n a l S o l i d - S t a t e C ir c u i t s C o n f e r e n c e 1 - 4 2 4 4 - 0 0 7 9 - 1 / 0 6 © 2 0 0 6 IEEE Authorized licensed use limited to: The University of Utah. Downloaded on May 17,2010 at 22:16:21 UTC from IEEE Xplore. Restrictions apply. ISSCC 2006 / SESSION 30 / SILICON FOR BIOLOGY / 30.2 Integrated Neural Interface IC Measured Performance Power/command signal frequency 2.64 MHz Minimum required receive coil voltage amplitude 5.7 V(peak) 3.3-V voltage regulator dropout (lL = 3 mA) 250 mV Load regulation (lL = 2-10 mA) 0.15 % Line regulation (Vunreg = 3.5 V - 8.0 V) <0.30 %/V Maximum command input data rate (ASK) 6.5 kbps Number of Channels/Electrodes 88 signal, 12 ground Neural Signal Amplifier Gain 60.1 dB (1.1 -5 kHz) Input Referred Noise 5.1 pVrms Individual Amplifier Supply Current 12.8 pA ADC resolution (LSB = 2.4 pV electrode referred) 9 bits ADC sampling rate 15.0 kSamples/s ADC INL/DNL error (codes 50-511) ±0.8 LSB/ ±0.6 LSB Spike detector threshold resolution (LSB = 4.8 pV electrode referred) 7 bits FSK data transmission frequency 433 MHz FSK data rate 330 kbps Received signal power at distance of 13 cm -86 dBm Total chip power dissipation 13.5 mW Total chip area (0.5-pm, 2P3M CMOS) 27.3 mm2 Figure 30.2.6: Table summarizing measured INI chip performance. • 2 0 0 6 IEEE I n t e r n a t io n a l S o l i d - S t a t e C ir c u i t s C o n f e r e n c e 1 - 4 2 4 4 - 0 0 7 9 - 1 / 0 6 © 2 0 0 6 IEEE Authorized licensed use limited to: The University of Utah. Downloaded on May 17,2010 at 22:16:21 UTC from IEEE Xplore. Restrictions apply. ISSCC 2006 / SESSION 30 / SILICON FOR BIOLOGY / 30.2 bridge rectifier and voltage regulator ASK command data receiver and controller 433-MHz, 330 kbps FSK data transmitter Figure 30.2.7: Die photo of 4.7x5.9mm2 integrated neural interface chip. Insets show FSK data transmitter with integrated 54 nH inductor (left) and neural amplifier/spike detector cell (right). • 2 0 0 6 IEEE I n t e r n a t io n a l S o l i d - S t a t e C ir c u i t s C o n f e r e n c e 1 - 4 2 4 4 - 0 0 7 9 - 1 / 0 6 © 2 0 0 6 IEEE Authorized licensed use limited to: The University of Utah. Downloaded on May 17,2010 at 22:16:21 UTC from IEEE Xplore. Restrictions apply.