A DRAM backend for the impulse memory system

Update item information
Publication Type technical report
School or College College of Engineering
Department Computing, School of
Program Advanced Research Projects Agency
Creator Zhang, Lixin
Title A DRAM backend for the impulse memory system
Date 1998-12-16
Description The Impulse Adaptable Memory System exposes DRAM access patterns not seen in conventional memory systems. For instance, it can generate 32 DRAM accesses each of which requests a four-byte word in 32 cycles. Conventional DRAM backends are optimized for accesses that request full cache lines. They may not be able to handle smaller accesses effectively. In this document, we describe and evaluate a DRAMbackend that reduces the average DRAMaccess latency by exploiting the potential parallelism of DRAM accesses in the Impulse system. We design the DRAM backend by studying each of its important design options: DRAM organization, hot row policy, dynamic reordering of DRAM accesses, and interleaving of DRAM banks. The experimental results obtained from the execution-driven simulator Paint [10] show that, compared to a conventional DRAM backend, the proposed backend can reduce the average DRAM access latency by up to 98%, the average memory cycles by up to 90%, and the execution time by up to 80%. This
Type Text
Publisher University of Utah
Subject Impulse Adaptable Memory System; DRAM
Subject LCSH Computer storage devices; Cache memory
Language eng
Bibliographic Citation Zhang, Lixin (2001). A DRAM backend for the impulse memory system. UUCS-00-002.
Series University of Utah Computer Science Technical Report
Rights Management ©University of Utah
Format Medium application/pdf
Format Extent 319,991 bytes
Identifier ir-main,60573
Source University of Utah School of Computing
ARK ark:/87278/s67w6wjv
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2021-05-06
ID 705044
Reference URL https://collections.lib.utah.edu/ark:/87278/s67w6wjv
Back to Search Results