Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Electrical & Computer Engineering |
Creator |
Myers, Chris J. |
Other Author |
Belluomini, Wendy |
Title |
Efficient timing analysis algorithms for timed state space exploration* |
Date |
1997 |
Description |
Abstract This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the synthesis procedure to optimize the design. Much of the computational complexity in the synthesis of timed circuits currently is in finding the reachable timed state space. We introduce new algorithms which utilize geometric regions to represent the timed state space and partial orders to minimize the number of regions necessary. These algorithms operate on specifications sufficiently general to describe practical circuits. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
First Page |
1 |
Last Page |
13 |
Language |
eng |
Bibliographic Citation |
Belluomini, W., & Myers, C. J. (1997). Efficient timing analysis algorithms for timed state space exploration. The Third International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1-13. April. |
Rights Management |
(c) 1997 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
161,783 bytes |
Identifier |
ir-main,15053 |
ARK |
ark:/87278/s6gt65k3 |
Setname |
ir_uspace |
ID |
704958 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6gt65k3 |