Floating gate common mode feedback circuit for low noise amplifiers

Most low noise amplifier designs focus on eliminating sources of noise that are intrinsic 1.0 the amplifier (thermal noise, Ilfnoise). As integrated (circuit design moves increasingly towards mixed signal implementations, the design of low-noise malog amplifiers must be re-evaluated to consider the switching noise generated by on-chip digital circuitry. We designed three fully differential versions of a previously reported single-ended low-noise amplifier for biomedical applications. Each design uses a different common mode feedback (CMFB) circuit. The first uses a standard continuous-time CMFB circuit, the second uSes a switched capacitor CMFB circuit, and the third uses a novel floating gate CMFB circuit. A test chip he3 been fabricated in a 1.5 pm CMOS process. Tha fully differential amplifiers outperform the single-ended amplifier in the presence of switching noise. The amplifier with the floating gate CMFB circuit has the lowest total harmonic distortion over the critical range and exhibits the smallest fluctuation in the common mode output level.

Authorized licensed use limited to: The University of Utah. Downloaded on May 19,2010 at 20:08:45 UTC from IEEE Xplore. Restrictions apply. A FLOATING GATE COMMON MODE FEEDBACK CIRCUIT FOR LOW NOISE . AMPLIFIERS Cameron T. Charles and Reid R. Harrison Department of Electrical and Computer Engineering University of Utah Salt Lake City, Utah, 84112, USA ABSTRACT Most low noise amplifier designs focus on eliminating sources of noise that are intrinsic to the amplifier (thennal noise, Ilfnoise). As integrated drcuit design moves increasingly towards mixed signal implementations, the design of low-noise analog amplifiers must be re...evaluated to consider the switching noise generated by on-<:hip digital circuitry. We designed three fully differential versions of a previously reported single-ended low·noise amplifier for biomedical applications. Each design uses a different common mode feedback (CMFB) circuit. The first uses a stmdard continuous-time CMFB circuit, the second uses a switched capacitor CMFB circuit, and the third lIses a novel floating gate CMFB circuit. A test chip has been fabricated in a 1.5 flm CMOS process. Th" fully differential amplifiers outperfonn the single·..,nded amplifier in the presence of switching noise. The amplifier with the floating gate CMFB circuit has the lowest total harmonic distortion over the critical range and exhibits the smallest fluctuation in the common mode output level. I. INTRODUCTION There are many applications in modem electronics where it is necessary to amplify low voltage signals while adding minimal noise. Most low noise amplifier designs focus on eliminating sources of' noise that are intrinsic to the amplifier (thennal noise, Ilf noise). As integrated circuit design moves increasingly towards mixed signal implementations, the design of low noise analog amplifiers must be re-evaluated to consider the switching noise generated by the on-chip digital circuitry. We designed a fully differential version of a previously reported single-ended low-noise amplifier (LNA) for biomedical applications [I]. The amplifier is fully integrated and is suitable for recording biological signals in the range from below I Hz to 7.2 kHz. The maj or difference between the design of a single ·ended amplifier and a fully differential amplifier is the need for a common mode feedback (CMFB) circuit in tho: lalter design. We designed three different versions of the fully differential LNA, each using a different CMFB circuit. 0·7803·7778·8/03/$17.00 ©20031EEE 180 The first uses a standard continuous-time CMFB circuit, the second uses a standard switched capacitor CMFB circuit, and the third uses a novel floating gate CMFB circuit. A floating gate CMFB circuit has been previously reported in [2]. however our circuit differs by using only one floating gate and making provision for tuning through setting the charge on the floating gate. Detailed characterization results were not given for the previous design, so we can not compare the perfonnance of the CMFB implementations. Many other variations of CMFB circuits have been proposed, including ones using resistive averaging for common mode detection, and multiple gain stages for a reduced common mode error voltage [3]. Detailed comparisons of many of the more common CMFB circuits are given in [4] and [5]. In this paper we demonstrate that our novel floating gate CMFB circuit has advantages over the two standard designs tested, and that the fully differential designs outperfonn the single-ended design in the presence of digital interference. This report is divided into six main sections. Section II summarizes the important design features of the LNA, which hold for all three of the fully differential amplifiers. Section III gives the circuit descriptions of the CMFB circuits used in the fully differential amplifielS. Section IV reports the simulation results that were obtained prior to fabricating the test chip. Section V reports the experimental results obtained from the test chip. Finally, section VI summarizes the findings and presents conclusions on the use of fully differential low noise amplifiers and the relative perfonnances of the CMFB circuits. II. AMPLIFIER DESIGN Figure I shows the schematic of the amplifier design. The midband gain AM is set by C1/C" and the bandwidth is gm/(AMCJ, where gm is the transconductance of the operational transconductance amplifier (OTA). Transistors M,·Md are MOS·bipolar devices acting as "pseudo-resistors" [6]. For small voltages across these devices, their incremental resistance is very high. Figure 2 shows the schematic of the OTA used in the amplifier, omitting the CMFB circuit. The circuit topology is a standard design suitable for driving SSMSD2003 Authorized licensed use limited to: The University of Utah. Downloaded on May 19,2010 at 20:08:45 UTC from IEEE Xplore. Restrictions apply. capacitive loads, but the sIzmg of the transistors is critical for achieving low noise at low current levels. The input transistors MJ and Ml are sized with a large W IL ratio to push them into weak inversion, maximizing their gmlID ratio. Transistors MrM9 are sized with a small W IL ratio to keep them in strong inversion, minimizing their gml/D ratio. Since the input-referred thermal noise power is expressed as v' ';Jh"ma' = 8kTy[1 + 2 gm3 + gm7 ] (I) gml gmt gml these size choices minimize thermal noise. An transistors are sized as large as possible to minimize II! noise. As devices ·M3-MS are made larger, their gate capacitances increase, which moves the secondary poles closer to the dominant pole created by CL. This reduces the phase margin, so the device sizes are chosen as a compromise between noise and stability. c, v~ -11----'----1 V~f-1l---r-I c, c, Figore I: Schematic of fully differential low noise amplifier v" Figure 2: Schematic of operational transconductance amplifier used in low noise amplifier 181 III. COMMON MODE FEED BACK CIRCUITS A. Continuous-Time Design Figure 3 shows the schematic of the continuous­time CMFB circuit [7]. If the common mode level ofthe outputs increases, the currents through Mn and MI5 increase, decreasing the currents through Mn and Mu. This causes Vcntrl to increase and reduces the common mode level of the outputs. The disadvantage of this design is the limited linear range of the differential input pairs formed by M12-M15. This restricts the allowable signal swing at the outputs. Our implementation maximizes the allowable signal swing by sizing MJ rMJ5 with a very small W IL ratio, thereby reducing their gm and increasing their linear range. B. Switched Capacitor Design Figure 4 shows the schematic of the switched capacitor CMFB circuit [7]. This circuit uses capacitive voltage division to average the output voltages and adds the appropriate bias voltage. If the common mode level of the outputs increases, the average voltage produced by the Cc capacitors increases, increasing Vmtrl and reducing the common mode level of the outputs. The Cs capacitors were chosen to be 115 the size of the Cc capacitors. This sizing is a compromise between larger capacitors which unnecessarily overload the OT A, and smaller capacitors which suffer from charge injection from the transiltor switches. The output signal swing is larger for this implementation than for the continuous­time implementation and is only limited by the transistor switches, since the capacitors are linear over the entire range of output voltages. The disadvantage of this design is that it can only be used in discrete time applications because of clock feed-through glitches. Figure 3: Schematic of continuous-time common mode feedback circuit Authorized licensed use limited to: The University of Utah. Downloaded on May 19,2010 at 20:08:45 UTC from IEEE Xplore. Restrictions apply. Figure 4: Switched capacitor common mode feedback circuit c. Floating Gate Design A floating gate is a polysilicon node surrounded by Si02, which traps charge on the gate indefinitely. Figure 5 shows the schematic of the floating gate CMFB circuit, omitting the circuiby for setting the charge on the floating gate. This design combines he advanta.ges of the two previous designs presented. The operation is similar to that of the switched capacitor CMFB c:ircuit. The voltage at node VI is set by a combination of the common mode level of the outputs and the stored charge on the floating gate node. The stored charge can be programmed to achieve the proper bias voltage for the desired common mode voltage, and the common mode voltage of the outputs is then fed back by the av",aging capacitors Cc to keep the common mode voltage at the desired level. Analyzing this circuit yields the following expression for v}: (2) (3) where Q is the stored charge on the floating gate node, and VREF is a reference voltage that is supplied to the circuit. It can be seen that VkEF and Q perform a similar role to M20 in the switched capacitor CMFB circuit. The· negative sign in front of the averaged output voltage is compensated for by MJ2 and MH • The circuitry for programming the floating gate charge is based on a design reported in [8], and a simplified version is shown in Figure 6 Electrons are removed from the floating gate using Fowler-Nordheim tunneling across the tunneling junction CrUN, The voltage needed to create an electric field large enough for this tunneling to take place is 25-35V in the 1.5 flm technology used for our chip, and is lower for smaller technologies with thinner oxides. The AND gate used to control the tunneling is • high voltage design which uses 182 nFETs with lightly doped drain regions (using well diffusion) that have breakdown voltages of over 45V. Electrons are added to the gate usiJg hot electron injection in a P'ET device, shown as MJ2 in Figure 6. The hot electron injection is controlled through the NAND gate. A VDS of 7-IOV is needed for hot electron injection to occur in the 1.5 flttl technology used for the test chip. Once the charge on the floating gate has been set, it will remain there indefinitely. Like the switched capacitor CMFB circuit, the floating gate circuit uses capacitors to achieve better linearity than the continuous-time circuit for large signal swings. Since no clock is needed, there is no digital switching noise, so this CMFB circuit can be used in either continuous or discrete time applications. Another advantage is that the charge on the floating gate can be set to eliminate any DC common mode offset. The only added complexities are that a stable V kEF must be provided and the charge on tile floating gate must be programmed. Different values of V REF are needed for circuit operation and for progr~mming the floating gate, so it could be switched between a bandgap voltage reference for nonnal operation and an arbitrary value for programming the floating gate. IV. SIMULATION RESULTS The circuits were simulated using the TSPICE simulator with a BSIM3v3 level 49 transistor model Programming of the floating gate through tunneling and Figure 5: Schematic of floating gate common mode feedback circuit :~~~ '=$3CT"' tunnel HV select inject select Figure 6: Simplified schematic of circuitry used for programming the floating gate Authorized licensed use limited to: The University of Utah. Downloaded on May 19,2010 at 20:08:45 UTC from IEEE Xplore. Restrictions apply. injection was not simulated. The trapped charge on the floating gate was simulated by specifYing an initial condition for the voltage, and the simulation was made to converge by connecting a very large resistance (>1020 ohms) from the floating gate node to ground. Figure 7 plots the common mode level of the outputs for each of the fully differential amplifiers for a 10 kHz input with 25 m V amplitude. The power supplies for the circuits are :1:2.5 V, and the gains are approximately 40 dB. From this plot it can be seen that the switched capacitor and floating gate CMFB circuits stabilize the common mode level of the outputs more effectively than the continuous-time CMFB circuit. v. EXPERIMENTAL RESULTS A test chip has been fabricated in a 1.5 ~ m CMOS process with the three versions of the fully differential output LNA, and the single-ended LNA. The fuIJy differential amplifiers are similar in size, and consume about 23% more area than the single-ended design they are based on. The chip includes a pin for injecting digital switching noise. The pin is connected to a wire running over the amplifier outputs. A die photograph of the chip is shown in Figure 8. The input-referred noise was similar for the floating gate and continuous fully differential amplifiers, at 2.5 ~ Vnns. This compares favorably to the single­ended amplifier, for which the input-referred noise was measured at 2.6 ~ Vrms. As expected, the input-referred noise for the switched capacitor fully differential amplifier was significantly higher (S.3 ~ Vrms) due to the digital switching noise of the switched capacitor components. To simulate the presence of digital noise on the chip, we injected a 1 kHz square wave of 2.5 V amplitude using the pin included for this purpose. In the presence of this digital interference, the benefits of the 0.2r-__ ~ __ ~--__ --_--.., 0.15 switched capacllor 0.1 Time (ms) Figure 7: Transient simulation of the common mode output levels of each amplifier 183 fully differential amplifiers were evident. The input­referred noise of the continuous and floating gate amplifiers increased from 2.5 to 2.6 ~ Vrms, while the input-referred noise of the single-ended amplifier increased from 2.6 to 4.S I'Vrrns. A good measurement of the nonlinear interaction between the common mode and differential mode components of an amplifier is the total harmonic distortion (THD) [S]. Figure 9 plots the THD of each of the fully differential amplifiers against the RMS voltage in the fundamental harmonic at 1 kHz. For RMS output voltages below 1.3 V, all of the amplifiers have similar performance, with a THD of < 0.5%. For RMS output voltages above this level, the floating gate amplifier has a lower THD than the other amplifiers. This range, from a THD of 0.5% to about 5%, is the critical range where the performance of the amplifiers will differ. For inputs below this range all of the amplifiers have negligible distortion, and for inputs above this range all of the amplifiers have too much distortion to be useful. The THD curves are not as widely separated as we would expect from measurements of the effectiveness of the different CMFB circuits at controlling the common mode level of the outputs. We suspect that this is due to the distortion from the amplifier core (Figure 2) overwhelming the distortion from the CMFB circuits for input signals in this range. Figure 10 displays the common mode output levels for each of the CMFB implementations for a 20 mV, I kHz input signal. The floating gate implementation had the smallest variance in the common mode output signal, with a peak to peak excursion of 3.8 mY, followed by the switched capacitor implementation at 15.2 mY. The continuous time version was much less effective at controlling the common mode output voltage, with a signal excursion of 220 m V peak to peak. The plot also shows that the floating gate implementation is the only one with the common mode output voltage centered around 0 V, since this can be tuned by setting the charge on the floating gate or by changing the reference voltage provided to the circuit (see figure S). Figure II displays similar results as Figure 10, but in the frequency domain. A differential mode input was applied to each of the amplifiers at varying frequencies, and the amplitudes of the common mode output fluctuations were measured, and are shown in Figure II. The input signal amplitude was 20 mY. The continuous CMFB performed worst with an average common mode output fluctuation of 188 mV peak to peak, followed by the switched capacitor CMFB with an average fluctuation of 13.4 mV peak to peak. The floating gate CMFB had the lowest average fluctuation at 2.2 m V peak· to peak Table 1 summarizes the characterization measurements for each of the amplifiers. Authorized licensed use limited to: The University of Utah. Downloaded on May 19,2010 at 20:08:45 UTC from IEEE Xplore. Restrictions apply. Figure 8: Test chip photograph 3.5 r.===;====;~-~-~-~-I'J -e- continuous I _ swUthed capacitor 3 __ floating gale i ~2.5 .2 ~ .~ 2 C ·~1.5 E • ~ .. ' :!! Amplitude of Fundamental Harmonic (d8Vrms) Figure 9: Measured total harmonic distortion at I KHz for each of the fully differential amplifiers Time (fI'Is) Figure 10: Measured common mode output levels of the amplifiers for a 20mV I kHz peak to peak input signal . i -g 10 , '5. ~ ~ 10. , o g " 5 10 , E E o " . " I-~ continuous _ switched capacitor ___ floating gate ~ ---- , " " , Frequency (Hz) Figure II: Measured differential input amplitude to common mode output ampJitude over frequency for each amplifier Parameter Continuou Switched Floating s-time capacitor gate Supply voltage ±2.SV ,,2.SV ±2.SV Supply Current' 36M 32M 37M Gain 39.4 dB 39.2 dB 39.3 dB Bandwidth 6.8 kHz 7.2 kHz 6.9 kHz Input-referred 2.S 5.3 2.S noise(uV rms) Dynamic range 76 dB 80 dB 77 dB (l%THD) CMRR (10 Hz- >83 dB >87 dB >91 dB S kHz) PSRR(lO Hz- >72 dB >73 dB >69dB S kHz) Area (I.S 1m 0.20S 0.207 0.212 mm' technology) mm2 mm2 Table I: Experimental measurements of amplifiers (* denotes measurement taken from simulation) VI. CONCLUSIONS We have designed and simulated a novel floating gate CMFB circuit. This circuit combines a large output 'signal swing with continuous-time operation. A test chip' has been fabricated, and experimental results demonstrate that the fully differential amplifier with the floating gate CMFB circuit has the lowest THD over the critical range. The use of the floating gate circuit provides the advantages of the switched capacitor CMFB circuit (i.e' l lower distortion~ larger output signal swing) with no switching noise, which aHows it to be used in continuous-time applications. We have also compared the noise 184 Authorized licensed use limited to: The University of Utah. Downloaded on May 19,2010 at 20:08:45 UTC from IEEE Xplore. Restrictions apply. performance of single-ended and fully differential versions of a LNA designed for biological signals. Noise perfonnance was similar in the absence of digital interference, but when an interfering digital signal was included, the fully differential versions had a clear performance advantage. vn. ACKNOWLEDGEMENTS This work was funded by an STTR grant through the NSF (PID - 2201089) in collaboration with Bionic Technologies, LLC, of Salt Lake City, Utah. VIII. REFERENCES [I] R.R. Harrison, "A low-power, low-noise CMOS amplifier for neural recording applications," Proc. of the 2002 IEEE Int. Symp. on Circuits and Systems, 5:197-200. [2] J. RamfrecAngulo and AJ. Lopez, "MITE Circuits: The Continuous-Time Counterpart to Switched­Capacitor Circuits," IEEE Transactions on Circuits and Systems-II, vol. 48, no. I, pp. 45-55,2001. [3] L Luh, J. Choma, Jr., and J. Draper, "A Continuous­Time Common-Mode Feedback Circuit (CMFB) for High-Impedance Current-Mode Applications," IEEE Trans. On Circuits and Systems-II, vol. 47, no. 4, pp. 363-369, 2000. [4] P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, 2001. [5] J.F. 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