Clocked and asynchronous FIFO characterization and comparison

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Publication Type Journal Article
School or College College of Engineering
Department Electrical & Computer Engineering
Creator Stevens, Kenneth
Other Author Han, HoSuk
Title Clocked and asynchronous FIFO characterization and comparison
Date 2009
Description Heterogeneous blocks, IP reuse, network-on-chip interconnect, and multi-frequency design are becoming more prevalent in integrated circuit design. Communication amongst these blocks typically employs first-in-first-out (FIFO) buffering for flow control. This paper characterizes and evaluates several common designs in order to determine which structure is best for various specific applications. Two clocked and four clockless asynchronous FIFO designs are compared varying capacity, bit width, and structural configurations. The FIFO layouts are characterized in the IBM 65nm 10sf process for latency, throughput, area, and power. First order models are created to aid in CAD for FIFO synthesis, modeling, and optimization. Comparative results show that the asynchronous designs uniformly out perform the clocked designs in nearly every aspect.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
Language eng
Bibliographic Citation Han, H. S., & Stevens, K. (2009). Clocked and asynchronous FIFO characterization and comparison. 17th IFIP/IEEE International Conference on Very Large Scale Integration. October.
Rights Management (c) 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Format Medium application/pdf
Format Extent 474,922 bytes
Identifier ir-main,15270
ARK ark:/87278/s6571wd0
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2021-05-06
ID 704829
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