Architectural synthesis of timed asynchronous systems

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Publication Type Journal Article
School or College College of Engineering
Department Electrical & Computer Engineering
Creator Myers, Chris J.
Other Author Bachman, Brandon M.; Zheng, Hao
Title Architectural synthesis of timed asynchronous systems
Date 1999
Description This paper describes a new method for architectural synthesis of timed asynchronous systems. Due to the variable delays associated with asynchronous resources, implicit schedules are created by the addition of supplementary constraints between resources. Since the number of schedules grows exponentially with respect to the size of the given data flow graph, pruning techniques are introduced which dramatically improve run-time without significantly affecting the quality of the results. Using a combination of data and resource constraints, as well as an analysis of bounded delay information, our method determines the minimum number of resources and registers needed to implement a given schedule. Results are demonstrated using some high-level synthesis benchmark circuits and an industrial example.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
Language eng
Bibliographic Citation Bachman, B. M., Zheng, H., & Myers, C. J. (1999). Architectural synthesis of timed asynchronous systems. IEEE International Conference on Computer Design (ICCD). October.
Rights Management (c) 1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Format Medium application/pdf
Format Extent 2,351,615 bytes
Identifier ir-main,15040
ARK ark:/87278/s6t731s7
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2021-05-06
ID 704764
Reference URL https://collections.lib.utah.edu/ark:/87278/s6t731s7
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