Precise exception handling for a self-timed processor

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Publication Type journal article
School or College College of Engineering
Department Kahlert School of Computing
Creator Brunvand, Erik L.
Other Author Richardson, William F.
Title Precise exception handling for a self-timed processor
Date 1995
Description Self-timed systems structured as multiple concurrent processes and communicating through self-timed queues are a convenient way to implement decoupled computer architectures. Machines of this type can exploit instruction level parallelism in a natural way, and can be easily modified and extended. However, providing a precise exception model for a self-timed micropipelined processor can be difficult, since the processor state does not change at uniformly discrete intervals. We present a precise exception method implemented for Fred, a self-timed, decoupled, pipelined computer architecture with out-of-order instruction completion.
Type Text
Publisher Institute of Electrical and Electronics Engineers (IEEE)
First Page 32
Last Page 37
Language eng
Bibliographic Citation Richardson, W. F., & Brunvand, E. L. (1995). Precise exception handling for a self-timed processor in Winner of best paper award in Design & Test track at ICCD95. IEEE Int inernational Conference on Computer Design (ICCD95), 32-7.
Rights Management (c) 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Format Medium application/pdf
Format Extent 735,967 bytes
Identifier ir-main,15751
ARK ark:/87278/s6h13k88
Setname ir_uspace
ID 703957
Reference URL https://collections.lib.utah.edu/ark:/87278/s6h13k88
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