Re-visiting the performance impact of microarchitectural floorplanning

Update item information
Publication Type Journal Article
School or College College of Engineering
Department Computing, School of
Creator Balasubramonian, Rajeev
Other Author Chakravorty, Anupam; Ranjan, Abhishek
Title Re-visiting the performance impact of microarchitectural floorplanning
Date 2006
Description The placement of microarchitectural blocks on a die can significantly impact operating temperature. A floorplan that is optimized for low temperature can negatively impact performance by introducing wire delays between critical pipeline stages. In this paper, we identify subsets of wire delays that can and cannot be tolerated. These subsets are different from those identified by prior work. This paper also makes the case that floorplanning algorithms must consider the impact of floorplans on bypassing complexity and instruction replay mechanisms.
Type Text
Publisher Workshop on Temperature Aware Computer Systems
Subject Microarchitectural floorplanning; Wire delays; Floorplanning algorithms; Microprocessor operating temperature; Critical loops; Pipelines
Subject LCSH Microprocessors
Language eng
Bibliographic Citation Chakravorty, A., Ranjan, A., & Balasubramonian, R. (2006). Re-visiting the performance impact of microarchitectural floorplanning. 3rd Workshop on Temperature Aware Computer Systems (TACS), held in conjunction with ISCA-33 , Boston, June.
Rights Management (c)Chakravorty, A., Ranjan, A., & Balasubramonian, R.
Format Medium application/pdf
Format Extent 90,747 bytes
Identifier ir-main,12008
ARK ark:/87278/s6f19gzn
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2012-06-13
ID 703798
Reference URL https://collections.lib.utah.edu/ark:/87278/s6f19gzn
Back to Search Results