Practical verification and synthesis of low latency asynchronous systems

A new theory and methodology for the practical verification and synthesis of asynchronous systems is developed to aid in the rapid and correct implementation of complex control structures. Specifications are based on a simple process algebra called CCS that is concise and easy to understand and use. A software prototype CAD tool called Analyze was written as part of this dissertation to allow the principles of this work to be tested and applied. Attention to complexity. efficient algorithms, and compositional methods has resulted in a tool that can be several orders of magnitude faster than currently available tools for comparable applications. A new theory for loose specifications based on partial orders is developed for both trace and bisimulation semantics. Formal verification uses these partial orders as the foundation of conformance between a specification and its refinement. The definitions support freedom of design choices by identifying the necessary behaviors. the illegal behaviors, and behaviors that are irrelevant. Loose specifications and their refinements are written using CCS semantics. Pure CCS has been modified so that all of the common asynchronous hazard models - delay insensitive, quasi delay insensitive, speed independent, and burst mode - can be supported by Analyze. The parallel composition semantics have been extended to allow conjunctive broadcast communication. These communication primitives are implemented in a mixed mode fashion so that pure CCS evaluation or hardware component modeling can be accomplished. A meta transition rule called computation interference is also implemented to strengthen the correctness of verifications under labeled transition systems such as CCS.