| Publication Type |
Journal Article |
| School or College |
College of Engineering |
| Department |
Computing, School of |
| Creator |
Brunvand, Erik L. |
| Other Author |
Khoche, Ajay |
| Title |
Critical hazard free test generation for asynchronous circuits |
| Date |
1997 |
| Description |
We describe a technique to generate critical hazard-free tests for self-timed control circuits build using a macromodule library, in a partial scan based DFT environment. We propose a 6 valued algebra to generate these tests which are guaranteed to be critical hazard free under an unbounded delay model. This algebra has been incorporated in a D-algorithm based automatic test pattern generator. |
| Type |
Text |
| Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
| First Page |
203 |
| Last Page |
208 |
| Language |
eng |
| Bibliographic Citation |
Khoche, A., & Brunvand, E. L. (1997). Critical hazard free test generation for asynchronous circuits. VLSI Test Symposium (VTS97), 203-8. |
| Rights Management |
(c)1997 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
| Format Medium |
application/pdf |
| Format Extent |
570,025 bytes |
| Identifier |
ir-main,15744 |
| ARK |
ark:/87278/s6n30f2q |
| Setname |
ir_uspace |
| ID |
702752 |
| Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6n30f2q |
