Stochastic cycle period analysis in timed circuits

This paper presents the stochastic cycle period as a performance metric for timed asynchronous circuits. The stochastic cycle period is a sum of weighted delays whose value represents the expected delay of a single cycle in the specification. Each weight denotes the amount of time a delay contributes to the cycle of the circuit when the circuit is in steady-state operation. This paper demonstrates how the stochastic cycle period is used to aggressively optimize timed circuits for average-case performance. It shows the use of the stochastic cycle period to restrict out low probability triggers, optimally order pins, and size transistors in gate implementations. All optimization efforts are focused to improve the average-case delay in the timed asynchronous circuit, at the possible expense of the worst-case delay. In addition, this paper shows the calculation of the stochastic cycle period and proposes a new method for calculating trigger probabilities in timed circuits. This new method is simulation based, does not require the timed state space of the specification, and can be applied to any arbitrary Petri not.