A cell set for self-timed design using actel FPGAs

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Publication Type technical report
School or College College of Engineering
Department Computing, School of
Creator Brunvand, Erik L.
Title A cell set for self-timed design using actel FPGAs
Date 1991
Description Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in a variety of applications. However, these systems require that suitable self-timed circuit primitives are available for building the system. This report describes a cell set designed for building self-timed circuits and systems using Actel field programmable gate arrays (FPGAs). The cells use a two-phase transition signalling protocol for control signals and a bundled protocol for data signals. This library of macro cells is designed to be used with the Workmen tool suite from VIEWlogic and the Action Logic System (ALS) from Actel.
Type Text
Publisher University of Utah
First Page 1
Last Page 33
Subject Self-timed systems; Actel field programmable gate arrays; FPGA
Subject LCSH Asynchronous circuits
Language eng
Bibliographic Citation Brunvand, E. (1991). A cell set for self-timed design using actel FPGAs. 1-33. UUCS-91-013.
Series University of Utah Computer Science Technical Report
Relation is Part of ARPANET
Rights Management ©University of Utah
Format Medium application/pdf
Format Extent 15,171,503 bytes
Identifier ir-main,16371
ARK ark:/87278/s6f76wnh
Setname ir_uspace
Date Created 2012-06-13
Date Modified 2021-05-06
ID 702592
Reference URL https://collections.lib.utah.edu/ark:/87278/s6f76wnh
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