Interfacing synchronous and asynchronous modules within a high-speed pipeline*

This paper describes a new technique for integrating asynchronous modules within CI high-speed synchronous pipeline. Our design eliminates potential metastability problems by using Q clock generated by Q stoppable rang oscillator, which is capable of driving the large clock load found in present day microprocessors. Using the ATACS design tool, we designed highly optimized transistor-level circuits to control the ring oscillator and generate the clock and handshake signals with minimal overhead. Our interface architecture requires no redesign of the synchronous circuitry. Incorporating asynchronous modules in a high-speed pipeline improves performance by exploiting data-dependent delay variations. Since the speed of the synchronous circuitry tracks the speed of the rang oscillator under different processes, temperatures, and voltages, the entire chap operates at the speed dictated by the current operating conditions, rather than being governed by the worst-case conditions. These two factors together can lead to a significant improvement an average-case performance. The interface design is tested using the 0.6um HP CMOS14B process in HSPICE.