Towards a formal model of shared memory consistency for intel itanium

We provide a simple formal model for ItaniumTM shared memory consistency [1, 2] covering a core set of instructions. Existing descriptions of Itanium shared memory consistency are based on an informal collection of ordering rules as well as several examples. Our operational model employs employs widely understood data structures such as buffers and memories, and expresses ordering constraints precisely using a collection of non-deterministic rules. This can enable the construction of reliable prototype implementations, formal verification against implementations, formal verification of synchronization routines. Our model covers all published ordering constraints, and also sheds light on tricky concepts such as causality.