| Publication Type |
Journal Article |
| School or College |
College of Engineering |
| Department |
Electrical & Computer Engineering |
| Creator |
Myers, Chris J. |
| Other Author |
Zhou, Bin; Yoneda,Tomohiro |
| Title |
Framework of timed trace theoretic verification revisited |
| Date |
2001 |
| Description |
This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification. |
| Type |
Text |
| Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
| First Page |
437 |
| Last Page |
442 |
| Language |
eng |
| Bibliographic Citation |
Zhou, B., Yoneda,T., & Myers, C. J. (2001). Framework of timed trace theoretic verification revisited. The Tenth Asian Test Symposium, 437-42. November. |
| Rights Management |
(c) 2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
| Format Medium |
application/pdf |
| Format Extent |
588,247 bytes |
| Identifier |
ir-main,15026 |
| ARK |
ark:/87278/s6sb4pv3 |
| Setname |
ir_uspace |
| ID |
702452 |
| Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6sb4pv3 |
