Synthesis, Verification and Optimization of Systolic Arrays

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Publication Type technical report
School or College College of Engineering
Department Computing, School of
Creator Rajopadhye, Sanjay Vishnu
Title Synthesis, Verification and Optimization of Systolic Arrays
Date 1986-12
Description Systolic arrays are a class of parallel architectures consisting of regular interconnections of a very large number of simple processors, each one operating on a small part of the problem. They are typically designed to be used as back-end. special-purpose devices for computation-intensive processing. Although the idea of using an array of identical machines for a computation is not new, recent advances in VLSI fabrication technology has spurred a great deal of pragmatic interest in such architectures. This dissertation addresses the issue of providing a sound theoretical basis for three important issues relating to systolic arrays, namely synthesis, verification and optimization.
Type Text
Subject computer architecture; systolic array; VLSI
Subject LCSH computer architecture; computer science
Language eng
Bibliographic Citation Rajopadhye, S. V. (1986). Synthesis, Verification and Optimization of Systolic Arrays.
Series University of Utah Computer Science Technical Report
Relation is Part of ARPANET
Format Medium application/pdf
Format Extent 62,919,528 bytes
File Name Rajopadhye-Synthesis_Verification.pdf
Conversion Specifications Original scanned with Kirtas 2400 and saved as 400 ppi uncompressed TIFF. PDF generated by Adobe Acrobat Pro X for CONTENTdm display
ARK ark:/87278/s65x4b58
Setname ir_computersa
Date Created 2016-05-25
Date Modified 2016-05-26
ID 101489
Reference URL https://collections.lib.utah.edu/ark:/87278/s65x4b58
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