Synthesis, Verification and Optimization of Systolic Arrays

Systolic arrays are a class of parallel architectures consisting of regular interconnections of a very large number of simple processors, each one operating on a small part of the problem. They are typically designed to be used as back-end. special-purpose devices for computation-intensive processing. Although the idea of using an array of identical machines for a computation is not new, recent advances in VLSI fabrication technology has spurred a great deal of pragmatic interest in such architectures. This dissertation addresses the issue of providing a sound theoretical basis for three important issues relating to systolic arrays, namely synthesis, verification and optimization.