Analyzing the Intel Itanium memory ordering rules using logic programming and SAT

We present a non-operational approach to specifying and analyzing shared memory consistency models. The method uses higher order logic to capture a complete set of ordering constraints on execution traces, in an axiomatic style. A direct translation of the semantics to a constraint logic programming language provides an interactive and incre- mental framework for exercising and verifying finite test programs. The framework has also been adapted to generate equivalent boolean satisfi- ability (SAT) problems. These techniques make a memory model spec- ification executable, a powerful feature lacked in most non-operational methods. As an example, we provide a concise formalization of the Intel Itanium memory model and show how constraint solving and SAT solv- ing can be effectively applied for computer aided analysis. Encouraging initial results demonstrate the scalability for complex industrial designs.