Publication Type |
Journal Article |
School or College |
College of Engineering |
Department |
Electrical & Computer Engineering |
Creator |
Myers, Chris J. |
Other Author |
Nelson, Curtis A.; Yoneda, Tomohiro |
Title |
Efficient verification of hazard-freedom in gate-level timed asynchronous circuits |
Date |
2007 |
Description |
Abstract-This paper presents an efficient method for verifying hazard-freedom in gate-level timed asynchronous circuits. Timed circuits are a class of asynchronous circuits that are optimized using explicit timing information. In asynchronous circuits, correct operation requires that there are no hazards in the circuit implementation. Therefore, when designing an asynchronous circuit, each internal node and output of the circuit must be verified for hazard-freedom to ensure correct operation. Current verification algorithms for timed circuits require an explicit state exploration that often results in state explosion for even modest-sized examples. The goal of this paper is to abstract the behavior of internal nodes and utilize this information to make a conservative determination of hazard-freedom for each node in the circuit. Experimental results indicate that this approach is substantially more efficient than existing timing verification tools. These results also indicate that this method scales well for large examples that could not be previously analyzed, in that it is capable of analyzing these circuits in less than a second. While this method is conservative in that some false hazards may be reported, our results indicate that their number is small. |
Type |
Text |
Publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
Volume |
26 |
Issue |
3 |
First Page |
592 |
Last Page |
605 |
Language |
eng |
Bibliographic Citation |
Nelson, C. A., Myers, C. J., & Yoneda, T. (2007). Efficient verification of hazard-freedom in gate-level timed asynchronous circuits. IEEE Transactions on CAD, 26(3), 592-605. March. |
Rights Management |
(c) 2007 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
Format Medium |
application/pdf |
Format Extent |
413,277 bytes |
Identifier |
ir-main,14973 |
ARK |
ark:/87278/s6x645dx |
Setname |
ir_uspace |
ID |
705296 |
Reference URL |
https://collections.lib.utah.edu/ark:/87278/s6x645dx |